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| M13S5121632A-2S Datasheet, PDF (4/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle | |||
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ESMT
M13S5121632A (2S)
Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on VDD & VDDQ supply relative to VSS
Voltage on inputs relative to VSS
Voltage on I/O pins relative to VSS
VDD, VDDQ
-1.0 ~ 3.6
V
VINPUT
-1.0 ~ 3.6
V
VIO
-0.5 ~ VDDQ+0.5
V
Operating ambient temperature
TA
0 ~ +70
°C
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
Short circuit current
PD
1
W
IOS
50
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Conditions & Specifications
DC Operation Conditions
Recommended operating conditions (Voltage reference to VSS = 0V)
Parameter
Symbol
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
VâI Matching: Pullup to Pulldown Current Ratio
Input leakage current: Any input 0V ï£ VIN ï£ VDD
(All other pins not tested under = 0V)
Output leakage current
(DQs are disable; 0V ï£ VOUT ï£ VDDQ)
VDD
VDDQ
VREF
VTT
VIH (DC)
VIL (DC)
VIN (DC)
VID (DC)
VI (Ratio)
IL
IOZ
Min
2.3
2.3
0.49*VDDQ
VREF - 0.04
VREF + 0.15
-0.3
-0.3
0.36
0.71
-2
-5
Max
2.7
2.7
0.51*VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
VDDQ + 0.3
VDDQ + 0.6
1.4
2
5
Unit Note
V
V
V
1
V
2
V
V
V
V
3
-
4
ïA
ïA
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
4/48
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