M13S5121632A-2S Datasheet, PDF (40/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S5121632A (2S)
Read Interrupted by a Write & Burst Terminate (@ BL=8, CL=3)
0
1
CLK
CLK
2
3
4
5
6
7
8
9
10
11
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
BAb
A10/AP
ADDR
(A0~An)
Ca
Cb
WE
DQS
DQ
DM
COMMAND
READ
Burst
Terminate
Qa0 Qa1
Db0 Db1 Db2 Db3 Db4 db5 Db6 Db7
WRITE
: Don’t care
10122B16R.B1
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2014
Revision : 1.1
40/48