PD488588 Datasheet, PDF (74/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
41. Glossary of Terms
ACT
activate
activate
adjacent
ASYM
ATTN
ATTNR
ATTNW
AV
bank
BC
BBIT
broadcast
BR
bubble
BYT
BX
C
CAL
CBIT
CCA
CCB
CFM,CFMN
Channel
CLRR
CMD
CNFGA
CNFGB
COL
COLC
COLM
column
Command
COLX
controller
COP
core
CTM, CTMN
Current control
Activate command from AV field.
To access a roe and place in sense amp.
To access a row and place in sense amp.
Two RDRAM banks which share sense amps
(also called doubled banks).
CCA register field for RSL VOL / VOH.
Power state – ready for ROW / COL packets.
Power state – transmitting Q packets.
Power state – receiving D packets.
Opcode field in ROW packets.
A block of 2 •2 ^{RBIT CBIT} storage cells in the core
of the RDRAM.
Bank address field in CLC packet.
CNFGA register field - # bank address bits.
An operation executed by all RDRAMs.
Bank address field in ROW packets.
Idle cycle(s) on RDRAM pins needed
because of a resource constraint.
CNFGB register field – 9 bits per byte.
Bank address field in COLX packet.
Column address field in COLC packet.
Calibrate (IOL) command in XOP field.
CNFGB register field - # column address bits.
Control register – current control A.
Control register – current control B.
Clock pins for receiving packets.
ROW / COL / DQ pins and external wires.
Clear reset command from SOP field.
CMOS pins for initialization / power control.
Control register with configuration fields.
Control register with configuration fields.
Pins for column-access control.
Column operation packet on COL pins.
Write mask packet on COL pins.
Rows in a bank or activated in sense amps
have 2^CBTI dualocts column storage.
A decoded bit-combination from a field.
Extended operation packet on COL pins.
A logic-device which drives the ROW / COL
/ DQ wires for a Channel of RDRAMs.
Column opcode field in COLC packet.
The banks and sense amps of an RDRAM.
Clock pins for transmitting packets.
Periodic operations to update the proper IOL
Value of RSL output drivers.
D
DBL
DC
device
DEVID
Write data packet on DQ pins.
CNFGB register field – doubled-bank.
Device address field in COLC packet.
An RDRAM on a Channel.
Control register with device address that is
matched against DR, DC, and DX fields.
DM
Device match for ROW packet decode.
Doubled-bank RDRAM with shared sense amp.
DQ
DQA and DQB pins.
DQA
Pins for data byte A.
DQB
Pins for data byte B.
DQS
NAPX register field – PDN/NAP exit.
DR,DR4T,DR4F Device address field and packet framing fields
in ROW and ROWE packets.
dualoct
DX
field
INIT
initialization
16 bytes – the smallest addressable datum.
Device address field in COLX packet.
A collection of bits in a packet.
Control register with initialization fields.
Configuring a Channel of RDRAMs so they
are ready to respond to transactions.
LSR
M
MA
MB
MSK
MVER
NAP
NAPR
NAPRC
NAPXA
NAPXB
NOCOP
NOROP
NOXOP
NSR
packet
PDN
PDNR
PDNXA
PDNXB
pin efficiency
PRE
PREC
precharge
PRER
CNFGA register field – low-power self-refresh.
Mask opcode field (COLM/COLX packet).
Field in COLM packet for masking byte A.
Field in COLM packet for masking byte B.
Mask command in M field.
Control register – manufacturer ID.
Power state – needs SCK/CMD wakeup.
Nap command in ROP field.
Conditional nap command in ROP field.
NAPX register field – NAP exit delay A.
NAPX register field – NAP exit delay B.
No-operation command in COP field.
No-operation command in ROP field.
No-operation command in XOP field.
INIT register field – NAP self-refresh.
A collection of bits carried on the Channel.
Power state – needs SCK/CMD wakeup.
Powerdown command in ROP field.
Control register – PDN exit delay A.
Control register – PDN exit delay B.
The fraction of non-idle cycles on a pin.
PREC, PRER, PREX precharge commands.
Precharge command in COP field.
Prepares sense amp and bank for activate.
Precharge command in ROP field.
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Data Sheet E0039N30 (Ver. 3.0)