PD488588 Datasheet, PDF (31/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
18. Interleaved RRWW - Example
Figure 18-1 shows a steady-state sequence of 2-dualoct RD/RD/WR/WR.. transactions directed to non-adjacent
banks of a single RDRAM. This is similar to the interleaved write and read examples in Figure 16-1 and Figure 17-1
except that bubble cycles need to be inserted by the controller at read/write boundaries. The DQ data pin efficiency
for the example in Figure 18-1 is 32/42 or 76%. If there were more RDRAMs on the Channel, the DQ pin efficiency
would approach 32/34 or 94% for the two-dualoct RRWW sequence (this case is not shown).
In Figure 18-1, the first bubble type tCBUB1 is inserted by the controller between a RD and WR command on the COL
pins. This bubble accounts for the round-trip propagation delay that is seen by read data, and is explained in detail in
Figure 4-1. This bubble appears on the DQA and DQB pins as tDBUB1 between a write data dualoct D and read data
dualoct Q. This bubble also appears on the ROW pins as tRBUB1.
The second bubble type tCBUB2 is inserted (as a NOCOP command) by the controller between a WR and RD
command on the COL pins when there is a WR-WR-RD sequence to the same device. This bubble enables write
data to be retired from the write buffer without being lost, and is explained in detail in Figure 15-2. There would be no
bubble if address c0 and address d0 were directed to different devices. This bubble appears on the DQA and DQB
pins as tDBUB2 between a write data dualoct D and read data dualoct Q. This bubble also appears on the ROW pins
as tRBUB2.
Figure 18-1 Interleaved RRWW Sequence with Two Dualoct Data Length
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃ T₂₄T₂₅ T₂₆ T₂₇T₂₈T₂₉ T₃₀ T₃₁ T₃₂T₃₃ T₃₄ T₃₅ T₃₆T₃₇ T₃₈ T₃₉ T₄₀T₄₁ T₄₂ T₄₃T₄₄T₄₅ T₄₆ T₄₇
CTM/CFM
ROW2
ACT a0
t_RBUB1
ACT b0
ACT c0
t_RBUB2
Transaction e can use the
same bank as transaction a
ACT d0
ACT e0
..ROW0
COL4
t_CBUB2
RD z1 RD z2
RD a1
RD a2
t_CBUB1
t_CBUB2
WR b1 WRA b2 WR c1 WRA c2 NOCOP NOCOP RDd0
RD f
..COL0
PREX z3
MSK (y2) PREX a3 MSK (b1) MSK (b2) MSK (c1) MSK (c2)
t_DBUB1
t_DBUB2
t_DBUB1
DQA8..0 D (y2)
Q (z1) Q (z2) Q (a1) Q (a2) D (b1) D (b2) D (c1) D (c2)
DQB8..0
Transaction y: WR
Transaction z: RD
Transaction a: RD
Transaction b: WR
Transaction c: WR
Transaction d: RD
Transaction e: RD
Transaction f: WR
y0 = {Da,Ba+4,Ry}
z0 = {Da,Ba+6,Rz}
a0 = {Da,Ba,Ra}
b0 = {Da,Ba+2,Rb}
c0 = {Da,Ba+4,Rc}
d0 = {Da,Ba+6,Rd}
e0 = {Da,Ba,Re}
f0 = {Da,Ba+2,Rf}
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
a1 = {Da,Ba,Ca1}
b1 = {Da,Ba+2,Cb1}
c1 = {Da,Ba+4,Cc1}
d1 = {Da,Ba+6,Cd1}
e1 = {Da,Ba,Ce1}
f1 = {Da,Ba+2,Cf1}
y2= {Da,Ba+4,Cy2}
z2= {Da,Ba+6,Cz2}
a2= {Da,Ba,Ca2}
b2= {Da,Ba+2,Cb2}
c2= {Da,Ba+4,Cc2}
d2= {Da,Ba+6,Cd2}
e2= {Da,Ba,Ce2}
f2= {Da,Ba+2,Cf2}
y3 = {Da,Ba+4}
z3 = {Da,Ba+6}
a3 = {Da,Ba}
b3 = {Da,Ba+2}
c3 = {Da,Ba+4}
d3 = {Da,Ba+6}
e3 = {Da,Ba}
f3 = {Da,Ba+2}
Data Sheet E0039N30 (Ver. 3.0)
31