PD488588 Datasheet, PDF (37/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
7.0 Other RDRAM Register Fields
This stage rewrites the INIT register with the final values of the LSR, NSR, and PSR fields.
In essence, the controller must read all the read-only configuration registers of all RDRAMs (or it must read the
SPD device present on each RIMM), it must process this information, and then it must write all the read-write
registers to place the RDRAMs into the proper operating mode.
Initialization Note :
1. During the initialization process, it is necessary for the controller to perform 128 current control operations
(3xCAL, 1xCAL/SAM) and one temperature calibrate operation (TCEN/TCAL) after reset or after powerdown
(PDN) exit.
2. The behavior of µPD488588 at initialization is as follows. It is distinguished by the "S28IECO" bit in the SPD.
S28IECO=1: Upon powerup, the device enters PDN state. The serial operations SETR, CLRR, and SETF
require a SDEVID match.
See the document detailing the reference initialization procedure for more information on how to handle this in
a system.
3. After the step of equalizing the total read delay of the RDRAM has been completed (i.e. after the TCDLY0 and
TCDLY1 fields have been written for the final time), a single final memory read transaction should be made to
the RDRAM in order to ensure that the output pipeline stages have been cleared.
4. The SETF command (in the serial SRQ packet) should only be issued once during the Initialization process,
as should the SETR and CLRR commands.
5. The CLRR command (in the serial SRQ packet) leaves some of the contents of the memory core in an
indeterminate state.
Data Sheet E0039N30 (Ver. 3.0)
37