PD488588 Datasheet, PDF (57/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
Notes 1. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is
effectively 0.0 to 0.0.
2. This parameter also applies to a -C80 or -C71 part when operated with tCYCLE = 3.33 ns.
3. This parameter also applies to a -C80 part when operated with tCYCLE = 2.81ns.
4. tS,MIN and tH,MIN for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3
specified tCYCLE values.
5. With VIL,CMOS = 0.5 VCMOS − 0.6 V and VIH,CMOS = 0.5 VCMOS + 0.6 V
6. Effective hold becomes tH4’=tH4 + [PDNXA • 64 • tSCYCLE + tPDNXB,MAX ] − [PDNX • 256 • tSCYCLE ]
if [PDNX • 256 • tSCYCLE ] < [PDNXA • 64 • tSCYCLE + tPDNXB,MAX ]. See Figure 23-4.
Data Sheet E0039N30 (Ver. 3.0)
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