PD488588 Datasheet, PDF (64/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
34. CMOS - Transmit Timing
Figure 34-1 is a timing diagram which shows the detailed requirements for the CMOS output signals. The SIO0
signal is driven once per tCYCLE1 interval on the falling edge. The clock-to-output window is tQ1,MIN /tQ1,MAX. The SCK
and SIO0 timing points are measured at the 50 % level. The rise and fall times of SIO0 are tQR1 and tQF1, measured at
the 20 % and 80 % levels.
Figure34-1 also shows the combinational path connecting SIO0 to SIO1 and the path connecting SIO1 to SIO0
(read data only). The tPROP1 parameter specified this propagation delay. The rise and fall times of SIO0 and SIO1
input must be tDR1 and tDF1, measured at the 20 % and 80 % levels. The rise and fall times of SIO0 and SIO1 outputs
are tQR1 and tQF1, measured at the 20 % and 80 % levels.
SCK
Figure 34-1 CMOS Timing - Data Signals for Transmit
t Q1,MAX
SIO0
t _HR,MIN
t _QR1
SIO0
or
SIO1
t _QF1
t _DR1
t _DF1
SIO0
or
SIO1
t _PROP1,MAX
t PROP1,MIN
t_QR1
t _QF1
64
Data Sheet E0039N30 (Ver. 3.0)
V_IH,CMOS
80%
50%
20%
V_IL,CMOS
V_OH,CMOS
80%
50%
20%
V_OL,CMOS
V_IH,CMOS
80%
50%
20%
V_IL,CMOS
V_OH,CMOS
80%
50%
20%
V_OL,CMOS