PD488588 Datasheet, PDF (60/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
31. RSL - Receive Timing
Figure 31-1 is a timing diagram which shows the detailed requirements for the RSL input signals on the Channel.
The DQA, DQB, ROW, and COL signals are inputs which receive information transmitted by a Direct RAC on the
Channel. Each signal is sampled twice per tCYCLE interval. The set/hold window of the sample points is tS/tH. The
sample points are centered at the 0 % and 50 % points of a cycle, measured relative to the crossing points of the
falling CFM clock edge. The set and hold parameters are measured at the VREF voltage point of the input transition.
The tDR and tDF rise- and fall-time parameters are measured at the 20 % and 80 % points of the input transition.
CFM
CFMN
DQA
DQB
ROW
COL
Figure 31-1 RSL Timing - Data Signals for Receive
VX-
VCM
VX+
0.5•t_CYCLE
t _DR
t_S t_H
t_S t_H
even
odd
t _DF
V _CIH
80%
50%
20%
V _CIL
V _DIH
80%
V_REF
20%
V_DIL
60
Data Sheet E0039N30 (Ver. 3.0)