PD488588 Datasheet, PDF (35/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
3.6 Write DEVID Register
The DEVID (device identification) register of the RDRAM is written with a unique address value so that
directed memory read and write transactions can be performed. This address value increases from 0 to 31.
The DEVID value is not necessarily the same as the SDEVID value. RDRAMs are sorted into regions of the
same core configuration (number of bank, row, and column address bits and core type).
3.7 Write PDNX, PDNXA Registers
The PDNX and PDNXA registers are written with values that are used to measure the timing intervals
connected with an exit from the PDN (powerdown) power state.
3.8 Write NAPX Register
The NAPX register is written with values that are used to measure the timing intervals connected with an exit
from the NAP power state.
3.9 Write TPARM Register
The TPARM register is written with values which determine the time interval between a COL packet with a
memory read command and the Q packet with the read data on the Channel. The values written set the
RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0.
3.10 Write TCDLY1 Register
The TCDLY1 register is written with values which determine the time interval between a COL packet with a
memory read command and the Q packet with the read data on the Channel. The values written set the
RDRAM to the minimum value permitted for the system. This will be adjusted later in stage 6.0.
3.11 Write TFRM Register
The TFRM register is written with a value that is related to the tRCD parameter for the system. The tRCD
parameter is the time interval between a ROW packet with an activate command and the COL packet with a
read or write command.
3.12 SETR/CLRR
First write the following registers with the indicated values:
TEST78
000416
TEST34
004016
Next, the RDRAM is given a SETR command and a CLRR command through the SIO block. This sequence
performs a second reset operation on the RDRAMs. Then the TEST34 and TEST78 registers are rewritten
with zero, in that order.
3.13 Write CCA and CCB Registers
These registers are written with a value halfway between their minimum and maximum values. This shortens
the time needed for the RDRAMs to reach their steady-state current control values in stage 5.0.
3.14 Powerdown Exit
The RDRAM is in the PDN power state at this point. A broadcast PDNExit command is performed by the SIO
block to place the RDRAMs in the RLX (relax) power state in which they are ready to receive ROW packets.
3.15 SETF
The RDRAM is given a SETF command through the SIO block. One of the operations performed by this step
is to generate a value for the AS (autoskip) bit in the SKIP register and fix the RDRAM to a particular read
domain.
Data Sheet E0039N30 (Ver. 3.0)
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