PD488588 Datasheet, PDF (65/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
35. RSL - Domain Crossing Window
When read data is returned by the RDRAM, information must cross from the receive clock domain (CFM) to the
transmit clock domain (CTM). The tTR parameter permits the CFM to CTM phase to vary though an entire cycle ; i.e.
there is no restriction on the alignment of these two clocks. A second parameter tDCW is needed in order to describe
how the delay between a RD command packet and read data packet varies as a function of the tTR value.
Figure 35-1 shows this timing for five distinct values of tTR. Case A (tTR=0) is what has been used throughout this
document. The delay between the RD command and read data is tCAC. As tTR varies from zero to tCYCLE (cases A
through E), the command to data delay is (tCAC-tTR). When the tTR value is in the range 0 to tDCW,MAX, the command to
data delay can also be (tCAC-tTR-tCYCLE). This is shown as cases A’ and B’ (the gray packets). Similarly, when the tTR
value is in the range (tCYCLE+tDCW,MIN) to tCYCLE, the command to data delay can also be (tCAC-tTR+tCYCLE). This is shown
as cases D’ and E’ (the gray packets). The RDRAM will work reliably with either the white or gray packet timing. The
delay value is selected at initialization, and remains fixed thereafter.
Figure 35-1 RSL Timing - Crossing Read Domains
CFM
COL
RDa1
CTM
DQA/B ^tTR
DQA/B
Case A t_TR=0
Case A' t_TR=0
CTM _tTR
DQA/B
DQA/B
Case B t _TR =tDCW,MAX
Case B' t _TR =t DCW,MAX
•••
•••
t_CAC -t _TR
t _CAC -t_TR-t_CYCLE
•••
t_CAC -t_TR
tCAC -tTR -t CYCLE
t _CYCLE
Q(a1)
Q(a1)
Q(a1)
Q(a1)
CTM
DQA/B
t_TR ^{Case C tTR =0.5•t CYCLE}
CTM
DQA/B
DQA/B
t _TR Case D
t_TR =t _CYCLE + t DCW,MIN
Case D'
t TR =t _CYCLE + t DCW,MIN
CTM
t _TR
DQA/B
Case E t TR =t CYCLE
DQA/B
Case E' t _TR =t CYCLE
•••
tCAC -tTR
•••
t _CAC -t_TR
tCAC -t TR +t CYCLE
•••
tCAC -t TR
t CAC -tTR+tCYCLE
Q(a1)
Q(a1)
Q(a1)
Q(a1)
Q(a1)
Data Sheet E0039N30 (Ver. 3.0)
65