PD488588 Datasheet, PDF (36/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
4.0 Controller Configuration
This stage initializes the controller block. Each step of this stage will set a field of the ConfigRMC[63:0] bus to the
appropriate value. Other controller implementations will have similar initialization requirements, and this stage
may be used as a guide.
4.1 Initial Read Data Offset
The ConfigRMC bus is written with a value which determines the time interval between a COL packet with a
memory read command and the Q packet with the read data on the Channel. The value written sets RMC.d1
to the minimum value permitted for the system. This will be adjusted later in stage 6.0.
4.2 Configure Row/Column Timing
This step determines the values of the tRAS,MIN , tRP,MIN , tRC,MIN , tRCD,MIN , tRR,MIN , and tPP,MIN RDRAM timing
parameters that are present in the system. The ConfigRMC bus is written with values that will be compatible
with all RDRAM devices that are present.
4.3 Set Refresh Interval
This step determines the values of the tREF,MAX RDRAM timing parameter that are present in the system. The
ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.
4.4 Set Current Control Interval
This step determines the values of the tCCTRL,MAX RDRAM timing parameter that are present in the system.
The ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.
4.5 Set Slew Rate Control Interval
This step determines the values of the tTEMP,MAX RDRAM timing parameter that are present in the system. The
ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.
4.6 Set Bank/Row/Col Address Bits
This step determines the number of RDRAM bank, row, and column address bits that are present in the
system. It also determines the RDRAM core types (independent, doubled, or split) that are present. The
ConfigRMC bus is written with a value that will be compatible with all RDRAM devices that are present.
5.0 RDRAM Current Control
This step causes the INIT block to generate a sequence of pulses which performs RDRAM maintenance
operations.
6.0 RDRAM Core, Read Domain Initialization
This stage completes the RDRAM initialization
6.1 RDRAM Core Initialization
A sequence of 192 memory refresh transactions is performed in order to place the cores of all RDRAMs into
the proper operating state.
6.2 RDRAM Read Domain Initialization
A memory write and memory read transaction is performed to the RDRAM to determine which read domain
the RDRAM occupies. The programmed delay of the RDRAM is then adjusted so the total RDRAM read delay
(propagation delay plus programmed delay) is constant. The TPARM and TCDLY1 registers of the RDRAM is
rewritten with the appropriate read delay values. The ConfigRMC bus is also rewritten with an updated value.
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Data Sheet E0039N30 (Ver. 3.0)