PD488588 Datasheet, PDF (25/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
13. Read Transaction - Example
Figure 13-1 shows an example of a read transaction. It begins by activating a bank with an ACT a0 command in an
ROWA packet. A time tRCD later a RD a1 command is issued in a COLC packet. Note that the ACT command
includes the device, bank, and row address (abbreviated as a0) while the RD command includes device, bank, and
column address (abbreviated as a1). A time tCAC after the RD command the read data dualoct Q (a1) is returned by
the device. Note that the packets on the ROW and COL pins use the end of the packet as a timing reference point,
while the packets on the DQA/DQB pins use the beginning of the packet as a timing reference point.
A time tCC after the first COLC packet on the COL pins a second is issued. It contains a RD a2 command. The a2
address has the same device and bank address as the a1 address (and a0 address), but a different column address.
A time tCAC after the second RD command a second read data dualoct Q(a2) is returned by the device.
Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank to precharge so
that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. The
a3 address includes the same device and bank address as the a0, a1, and a2 addresses. The PRER command
must occur a time tRAS or more after the original ACT command (the activation operation in any DRAM is destructive,
and the contents of the selected row must be restored from the two associated sense amps of the bank during the
tRAS interval). The PRER command must also occur a time tRDP or more after the last RD command. Note that the
tRDP value shown is greater than the tRDP,MIN specification in “36.Timing Parameters”. This transaction example reads
two dualocts, but there is actually enough time to read three dualocts before tRDP becomes the limiting parameter
rather than tRAS. If four dualocts were read, the packet with PRER would need to shift right (be delayed) by one tCYCLE
(note-this case is not shown).
Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT command must
occur a time tRC or more after the first ACT command and a time tRP or more after the PRER command. This ensures
that the bank and its associated sense amps are precharged. This example assumes that the second transaction
has the same device and bank address as the first transaction, but a different row address. Transaction b may not
be started until transaction a has finished. However, transactions to other banks or other devices may be issued
during transaction a.
Figure 13-1 Read Transaction Example
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃ T₂₄T₂₅ T₂₆ T₂₇T₂₈T₂₉ T₃₀ T₃₁ T₃₂T₃₃ T₃₄ T₃₅ T₃₆T₃₇ T₃₈ T₃₉ T₄₀T₄₁ T₄₂ T₄₃T₄₄T₄₅ T₄₆ T₄₇
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
ACT a0
t_RC
PRER a3
ACT b0
t_RAS
t_RP
RD a1 RD a2
t_RCD
t_CC
t_RDP
Q (a1)
Q (a2)
Transaction a: RD
Transaction b: xx
t_CAC
t_CAC
a0 = {Da,Ba,Ra}
b0 = {Da,Ba,Rb}
a1 = {Da,Ba,Ca1}
a2 = {Da,Ba,Ca2}
a3 = {Da,Ba}
Data Sheet E0039N30 (Ver. 3.0)
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