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| PD488588 Datasheet, PDF (53/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM | |||
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µPD488588
Figure 24-1 REFA/REFP Refresh Transaction Example
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43T44T45 T46 T47
CTM/CFM
ROW2
REFA a0
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
ACT b0
tRR
tRC
tRAS
REFP a1
ACT c0
tRP
tREF/2BBIT+RBIT
REFA d0
Transaction a: REFA
Transaction b: xx
Transaction c: xx
Transaction d: REFA
a0 = {Broadcast,Ba,REFR}
b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb}
c0 = {Dc, ==Ba, Rc}
d0 = {Broadcast,Ba+1,REFR}
a1 = {Broadcast,Ba}
BBIT = #bank address bits
RBIT = #row address bits
REFB = REFB3..REFB0
REFR = REFR8..REFR0
Figure 24-2 NAP/PDN Exit - tBURST Requirement
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43T44T45 T46 T47
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
tCE
ROP
t BURST
restricted ROP
COP
XOP
tS4 tH4
restricted
tS4 tH4
COP
XOP
REFA b12
REFA b31
32 bank refresh sequence
SCK
CMD
01
SIO0
SIO1
Note 1
0/1
The packet is repeated
from SIO0 to SIO1
Note 1
0/1
Power
State
NAP/PDN
Note 2
Note 2
DQS=0 DQS=1
(NAPXâ¢tSCYCLE)/(256â¢PDNXâ¢t SCYCLE)
STBY
Notes 1. Use 0 for NAP exit, 1 for PDN exit
2. Device selection timing slot is selected by DQS field of NAPX register
Data Sheet E0039N30 (Ver. 3.0)
53
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