PD488588 Datasheet, PDF (61/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
32. RSL - Transmit Timing
Figure 32-1 is a timing diagram which shows the detailed requirements for the RSL output signals on the Channel.
The DQA and DQB signals are outputs to transmit information that is received by a Direct RAC on the Channel.
Each signal is driven twice per tCYCLE interval. The beginning and end of the even transmit window is at the 75 %
point of the previous cycle and at the 25 % point of the current cycle. The beginning and end of the odd transmit
window is at the 25 % point and at the 75 % point of the current cycle. These transmit points are measured relative to
the crossing points of the falling CTM clock edge. The size of the actual transmit window is less than the ideal
tCYCLE/2, as indicated by the non-zero valued of tQ,MIN and tQ,MAX. The tQ parameters are measured at the 50 % voltage
point of the output transition.
The tQR and tQF rise- and fall-time parameters are measured at the 20 % and 80 % points of the output transition.
CTM
CTMN
DQA
DQB
Figure 32-1 RSL Timing - Data Signals for Transmit
VX-
0.75•t _CYCLE
tQR
VCM
VX+
t_Q,MAX
0.75•t _CYCLE
0.25•t CYCLE
t_Q,MIN t_Q,MAX
t_Q,MIN
even
odd
t _QF
V_CIH
80%
50%
20%
V_CIL
V_QH
80%
50%
20%
V_QL
Data Sheet E0039N30 (Ver. 3.0)
61