PD488588 Datasheet, PDF (48/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
Figure 23-1 summarizes the transition conditions needed for moving between the various power states. Note that
NAP and PDN have been divided into two substates (NAP-A/NAP-S and PDN-A/PDN-S) to account for the fact that a
NAP or PDN exit may be made to either ATTN or STBY states.
ATTNR
automatic
automatic
Figure 23-1 Power State Transition Diagram
ATTNW
ATTN
STBY
NAPR • RLXR
PDEV.CMD•SIO0
NAPR • RLXR
PDEV.CMD•SIO0
tNLIMIT
NAP-A
NAP
NAP-S
PDNR • RLXR
PDEV.CMD•SIO0
PDNR • RLXR
PDEV.CMD•SIO0
PDN-A
PDN
PDN-S
SETR/CLRR
Notation:
SETR/CLRR - SETR/CLRR Reset sequence in SRQ packet
PDNR - PDNR command in ROWR packet
NAPR - NAPR command in ROWR packet
RLXR - RLX command in ROWR packet
RLX - RLX command in ROWR,COLC,COLX packets
SIO0 - SIO0 input value
PDEV.CMD - (PDEV=DEVID)•(CMD=01)
ATTN - ROWA packet(non-broadcast) or ROWR packet
(non-broadcast) with ATTN command
At initialization, the SETR/CLRR Reset sequence will put the RDRAM into PDN-S state. The PDN exit sequence
involves an optional PDEV specification and bits on the CMD and SIOIN pins.
Once the RDRAM is in STBY, it will move to the ATTN/ATTNR/ATTNW states when it receives a non-broadcast
ROWA packet or non-broadcast ROWR packet with the ATTN command. The RDRAM returns to STBY from these
three states when it receives a RLX command. Alternatively, it may enter NAP or PDN state from ATTN or STBY
states with a NAPR or PDNR command in an ROWR packet. The PDN or NAP exit sequence involves an optional
PDEV specification and bits on the CMD and SIO0 pins. The RDRAM returns to the ATTN or STBY state it was
originally in when it first entered NAP or PDN.
An RDRAM may only remain in NAP state for a time tNLIMIT. It must periodically return to ATTN or STBY.
The NAPRC command causes a napdown operation if the RDRAM’s NCBIT is set. The NCBIT is not directly visible.
It is undefined on reset. It is set by a NAPR command to the RDRAM, and it is cleared by an ACT command to the
RDRAM. It permits a controller to manage a set of RDRAMs in a mixture of power states.
STBY state is the normal idle state of the RDRAM. In this state all banks and sense amps have usually been left
precharged and ROWA and ROWR packets on the ROW pins are being monitored. When a non-broadcast ROWA
packet or non-broadcast ROWR packet(with the ATTN command) packet addressed to the RDRAM is seen, the
RDRAM enters ATTN state (see the right side of Figure 23-2). This requires a time tSA during which the RDRAM
activates the specified row of the specified bank. A time TFRM•tCYCLE after the ROW packet, the RDRAM will be able
to frame COL packets (TFRM is a control register field – see Figure 22-1(5/7) “TFRM Register”). Once in ATTN
state, the RDRAM will automatically transition to the ATTNW and ATTNR states as it receives WR and RD
commands.
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Data Sheet E0039N30 (Ver. 3.0)