PD488588 Datasheet, PDF (45/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
Figure 22-1 Control Registers (6/7)
Control Register : TCDLY1
Address : 04a16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TCDLY1
Read/write register.
Reset value is undefined.
Field
TCDLY1
Description
Specifies the value of the tCDLY1-C core parameter in tCYCLE units. This adds a programmable delay to Q (read data)
packets, permitting round trip read to delay all devices to be equalized. This field may be written with the values “000”
(0•tCYCLE) through “010” (2•tCYCLE). Refer to TPARM Register for more details.
Control Register : SKIP
Address : 04b16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
AS MSE MS
0
0
0
0
0
0
0
0
0
0
Read/write register (except AS field).
Reset value is zero (SIO Reset).
Field
MS
MSE
AS
Description
Manual skip (MS must be 1 when MSE=1). > During initialization, the RDRAMs at the furthest point in the fifth read
domain may have selected the AS=0 value, placing them at the closest point in a sixth read domain. Setting the
MSE/MS fields to 1/1 overrides the autoskip value and returns them to the furthest point of the fifth read domain.
Manual skip enable (0=auto, 1=manual ).
Autoskip. Read-only value determined by autoskip circuit and stored when SETF serial command is received by
RDRAM during initialization. In Figure34-1, AS=1 corresponds to the early Q(a1) packet and AS=0 to the Q(a1) packet
one tCYCLE later for the four uncertain cases.
Control Register : TCYCLE
Address : 04c16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
TCYCLE13..0
Read/write register.
Reset value is undefined.
Field
TCYCLE13..0
Description
Specifies the value of the tCYCLE datasheet parameter in 64ps units. For the tCYCLE,MIN of 2.50 ns (2500ps), this field
should be written with the value “0002716” (39•64ps).
Data Sheet E0039N30 (Ver. 3.0)
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