PD488588 Datasheet, PDF (50/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
The RDRAM may be in ATTN or STBY state when the PDNR command is issued. When PDN state is exited, the
RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is
specified with PDNR, then the RDRAM will return to STBY state when PDN is exited. The current- and slew-rate-
control levels are re-established.
The RDRAM’s write buffer must be retired with the appropriate COP command before NAP or PDN are entered.
Also, all the RDRAM’s banks must be precharged before NAP or PDN are entered. The exception to this is if NAP is
entered with the NSR bit of the INIT register cleared(disabling self-refresh in NAP). The commands for relaxing,
retiring, and precharging may be given to the RDRAM as late as the ROPa0, COPa0, and XOPa0 packets in Figure
23-3. No broadcast packets nor packets directed to the RDRAM entering NAP or PDN may overlay the quiet window.
This window extends for a time tNPQ after the packet with the NAPR or PDNR command.
Figure 23-4 shows the NAP and PDN exit sequences. These sequences are virtually identical; the minor
differences will be highlighted in the following description.
Before NAP or PDN exit, the CTM/CFM clock must be stable for a time tCE. Then, on a falling and rising edge of
SCK, if there is a “01” on the CMD input, NAP or PDN state will be exited. Also, on the falling SCK edge the SIO0
input must be at a 0 for NAP exit and 1 for PDN exit.
If the PSX bit of the INIT register is 0, then a device PDEV5..0 is specified for NAP or PDN exit on the DQA5..0 pins.
This value is driven on the rising SCK edge 0.5 or 1.5 SCK cycles after the original falling edge, depending upon the
value of the DQS bit of the NAPX register. If the PSX bit of the INIT register is 1, then the RDRAM ignores the
PDEV5..0 address packet and exits NAP or PDN when the wake-up sequence is presented on the CMD wire. The
ROW and COL pins must be quiet at a time tS4 / tH4 around the indicated falling SCK edge(timed with the PDNX or
NAPX register fields). After that, ROW and COL packets may be directed to the RDRAM which is now in ATTN or
STBY state.
Figure 23-5 shows the constraints for entering and exiting NAP and PDN states. On the left side, an RDRAM exits
NAP state at the end of cycle T3. This RDRAM may not re-enter NAP or PDN state for an interval of tNU0. The RDRAM
enters NAP state at the end of cycle T13. This RDRAM may not re-exit NAP state for an interval of tNU1. The equations
for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. NAPX is the
value in the NAPX field in the NAPX register.
On the right side of Figure23-4, an RDRAM exits PDN state at the end of cycle T3. This RDRAM may not re-enter
PDN or NAP state for an interval of tPU0. The RDRAM enters PDN state at the end of cycle T13. This RDRAM may not
re-exit PDN state for an interval of tPU1. The equations for these two parameters depend upon a number of factors,
and are shown at the bottom of the figure. PDNX is the value in the PDNX field in the PDNX register.
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Data Sheet E0039N30 (Ver. 3.0)