PD488588 Datasheet, PDF (43/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
Figure 22-1 Control Registers (4/7)
Control Register : NAPX
Address : 04516
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0 DQS
NAPX4..0
NAPXA4..0
Read/write register.
Reset value is undefined.
Note tSCYCLE is tCYCLE1 (SCK cycle time).
Field
DQS
NAPX4..0
NAPXA4..0
Description
DQ Select. This field specifies the number of SCK cycles (0 ≥ 0.5 cycles, 1 ≥ 1.5 cycles) between the CMD pin
framing sequence and the device selection on DQ5..0. see Figure 23-4. This field must be written with a ”1” for this
RDRAM.
Nap Exit Phase A plus B. This field specifies the number of SCK cycles during the first plus second phases for exiting
NAP mode. It must satisfy:
NAPX•tSCYCLE ≥ NAPXA•tSCYCLE+tNAPXB,MAX
Do not set this field to zero.
Nap Exit Phase A. This field specifies the number of SCK cycles during the first phase for exiting NAP mode. It must
satisfy:
NAPXA•tSCYCLE ≥ tNAPXA,MAX
Do not set this field to zero.
Control Register : PDNXA
Address : 04616
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
PDNXA12..0
Read/write register.
Reset value is undefined.
Field
PDNXA4..0
Description
PDN Exit Phase A. This field specifies the number of (64•SCK cycle) units during the first phase for exiting PDN
mode. It must satisfy:
PDNXA•64•tSCYCLE ≥ tPDNXA,MAX
Do not set this field to zero.
Note – only PDNXA4..0 are implemented.
Note – tSCYCLE is tCYCLE1 (SCK cycle time).
Control Register : PDNX
Address : 04716
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
PDNX12..0
Read/write register.
Reset value is undefined.
Field
PDNX2..0
Description
PDN Exit Phase A puls B. This field specifies the number of (256•SCK cycle) units during the first plus second phases
for exiting PDN mode. It should satisfy:
PDNX•256•tSCYCLE ≥ PDNXA•64•tSCYCLE+tPDNXB,MAX
It this equation can’t be satisfied, then the maximum PDNX value should be written, and the tS4 / tH4 timing window will
be modified (see Figure 23-4).
Do not set this field to zero.
Note – only PDNX2..0 are implemented.
Note – tSCYCLE is tCYCLE1 (SCK cycle time).
Data Sheet E0039N30 (Ver. 3.0)
43