PD488588 Datasheet, PDF (15/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
Figure 5-1 Mapping between COLM Packet and D Packet for WR Command
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃ T₂₄T₂₅ T₂₆ T₂₇T₂₈T₂₉ T₃₀ T₃₁ T₃₂T₃₃ T₃₄ T₃₅ T₃₆T₃₇ T₃₈ T₃₉ T₄₀T₄₁ T₄₂ T₄₃T₄₄T₄₅ T₄₆ T₄₇
CTM/CFM
ROW2
..ROW0
ACT a0
COL4
..COL0
DQA8..0
DQB8..0
Transaction a: WR
WR a1
t_RTR
retire (a1)
MSK (a1)
t_CWD
D (a1)
PRER a2
ACT b0
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a3 = {Da,Ba}
COLM Packet
D Packet
T₁₇
T₁₈
T₁₉
T₂₀
T₁₉
T₂₀
T₂₁
T₂₂
CTM/CFM
CTM/CFM
COL4
COL3
COL2
COL1
COL0
MA7 MA5 MA3 MA1
M=1 MA6 MA4 MA2 MA0
MB7 MB4 MB1
MB6 MB3 MB0
MB5 MB2
DQB8 DB8 DB17 DB26 DB35 DB45 DB53 DB62 DB71
DQB7
•
•
•
DQB1
DB7 DB16 DB25 DB34 DB44 DB52 DB61 DB70
DB1 DB10 DB19 DB28 DB37 DB46 DB55 DB64
DQB0 DB0 DB9 DB18 DB27 DB36 DB45 DB54 DB63
When M=1, the MA and MB
fields control writing of
individual data bytes.
When M=0, all data bytes are
written unconditionally.
Each bit of the MB7..MB0 field
controls writing (=1) or no writing
(=0) of the indicated DB bits when
the M bit of the COLM packet is one.
DQA8
MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7
DA8 DA17 DA26 DA35 DA45 DA53 DA62 DA71
DQA7
•
•
•
DQA1
DA7 DA16 DA25 DA34 DA44 DA52 DA61 DA70
DA1 DA10 DA19 DA28 DA37 DA46 DA55 DA64
Each bit of the MA7..MA0 field
DQA0
controls writing (=1) or no writing
(=0) of the indicated DA bits when
the M bit of the COLM packet is one.
DA0 DA9 DA18 DA27 DA36 DA45 DA54 DA63
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7
Data Sheet E0039N30 (Ver. 3.0)
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