PD488588 Datasheet, PDF (62/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM

µPD488588
33. CMOS - Receive Timing
Figure 33-1 is a timing diagram which shows the detailed requirements for the CMOS input signals.
The CMD and SIO0 signals are inputs which receive information transmitted by a controller (or by another RDRAM’s
SIO1 output). SCK is the CMOS clock signal driven by the controller. All signals are high true.
The cycle time, high phase time, and low phase time of the SCK clock are tCYCLE1, tCH1 and tCL1, all measured at the
50 % level. The rise and fall times of SCK, CMD, and SIO0 are tDR1 and tDF1, measured at the 20 % and 80 % levels.
The CMD signal is sampled twice per tCYCLE1 interval, on the rising edge (odd data) and the falling edge (even data).
The set/hold window of the sample points is tS1/tH1. The SCK and CMD timing points are measured at the 50 % level.
The SIO0 signal is sampled once per tCYCLE1 interval on the falling edge. The set/hold window of the sample points
is tS2/tH2. The SCK and SIO0 timing points are measured at the 50 % level.
SCK
Figure 33-1 CMOS Timing - Data Signals for Receive
t _DR2
t _DF2
CMD
t_DR2
tCYCLE1
t _CH1
t _CL1
t_S1 t_H1
t_S1 t_H1
even
odd
t _DR1
SIO0
t _DF2
t_S2 t_H2
t _DF1
V _IH,CMOS
80%
50%
20%
V _IL,CMOS
V_IH,CMOS
80%
50%
20%
V_IL,CMOS
V _IH,CMOS
80%
50%
20%
V_IL,CMOS
62
Data Sheet E0039N30 (Ver. 3.0)