STC5423 Datasheet, PDF (9/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Register Map
STC5423
Synchronous Clock for SETS
Data sheet
Table 2: Register Map
Addr
0x00
0x01
0x02
0x03
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x18
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F¹
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
Reg Name
Chip_ID
Chip_Rev
Chip_Sub_Rev
Fill_Obs_Window
Leak_Obs_Window
Bucket_Size
Assert_Threshold
De_Assert_Threshold
Freerun_Cali
Disqualification_Range
Qualification_Range
Qualification_Soaking_Time
Ref_Index_Selector
Ref_Info
Ref_Activity
Ref_Qual
Interrupt_Event_Status
Interrupt_Event_Enable
Interrupt_Config
Hard_Wired_Switch_Pre_Selection
SRCSW_States
T0/T4_Tag_Select
Control_Mode
Loop_Bandwidth
Auto_Elect_Ref
Manual_Select_Ref
Selected_Ref
Device_Holdover_History
Long_Term_Accu_History
Bits
15-0
7-0
7-0
3-0
3-0
5-0
5-0
5-0
10-0
9-0
9-0
5-0
3-0
15-0
1-0
1-0
7-0
7-0
1-0
7-0
0
0
7, 5-
2, 0
7-0
3-0
3-0
3-0
31-0
31-0
Type
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R
R
R
Chip ID = 0x5423
Description
Chip revision number
Chip sub-revision number
Activity monitor: Leaky bucket fill observation window
Activity monitor: Leaky bucket leak observation window
Activity monitor: Leaky bucket size
Activity monitor: Leaky bucket alarm assert threshold
Activity monitor: Leaky bucket alarm de-assert threshold
Freerun calibration, 2’s complement, -102.4 to +102.3 ppm, step in
0.1ppm
Reference disqualification range, 0 ~ 102.3 ppm. The value is also
specified as pull-in range
Reference qualification range, 0 ~102.3 ppm.
Reference qualification soaking time, 0 ~ 63s
Determines which reference data is shown in register Ref_Info.
Frequency offset and frequency of the reference with index selected
by register Ref_Infor_Selector
Reference activity for reference 1 and 2
Reference 1 and 2 qualification
Interrupt events
Selects which of interrupt events will assert pin EVENT_INTR
Pin EVENT_INTR configuration and idle mode
Pre-selects reference number 1 and reference number 2 for hard-
wired manual switch mode
Indicates the status of pin SRCSW
Selects registers between T0 and T4 for register 0x20 - 0x3F
Frame phase align, Mode of Holdover, Revertive, Manual/Auto,
OOP, SRCSW
Loop bandwidth selection
Indicates the reference input elected by auto reference elector
The reference specified by users for manual selection mode
Indicates the PLL current selected reference
Device Holdover History
Long term Accumulated History
Page 9 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011