STC5423 Datasheet, PDF(14/60 Page) Connor-Winfield Corporation

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STC5423 Datasheet, PDF (14/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

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STC5423

Synchronous Clock for SETS

Data sheet

General Description

Application

The STC5423 is a single chip solution for the syn-

chronous clock in SDH (SETS), SONET, and Syn-

chronous Ethernet network elements. The device is

fully compliant with ITU-T G.813 (option1 and option

2), G.8262 EEC (option1 and option2), Telcordia

GR1244, and GR253 (Stratum3/4E/4/SMC). Its highly

integrated design implements all necessary reference

selection, monitoring, filtering, synthesis, and control

functions. An external oscillator (e.g., high precision

OCXO or TCXO) completes a system level solution

(see Functional Block Diagram, Figure 1). The

STC5423 has four different frequencies options of

external oscillator. The STC5423 supports multiple-

master operation for redundant application.

Overview

The STC5423 accepts 2 reference inputs and gener-

ates 9 synchronized clock outputs, including 2 frame

pulse clock outputs at 8kHz and 2kHz. Two indepen-

dent PLL-based timing generators, T0 and T4, pro-

vide the essential functions for Synchronous

Equipment Timing Sources (SETS). T0 controls syn-

thesizer G1~G7, and synthesizer F. T4 controls syn-

thesizer GT4. Clock outputs CLK1~CLK7 can be

derived from synthesizer G1~G7, respectively.

CLK3~CLK7 can also be derived from synthesizer

GT4 from T4 path. Frame pulse clock outputs are

derived from synthesizer F. The STC5423 incorpo-

rates a microprocessor interface, which can be con-

figured for all common microprocessor interface

types.

Chip Master Clock

The STC5423 operates with an external oscillator

(e.g., OCXO or TCXO) as its master clock. The

device supports four different frequencies of master

clock: 10MHz, 12.8MHz, 19.2MHz, and 20MHz. Initial

default accepted frequency is 12.8MHz.

Reference Inputs

The STC5423 accepts 2 reference inputs which sup-

port frequencies range from 8kHz to 125MHz. The

two reference inputs are continuously frequency auto-

detected, activity and quality monitored. The activity

monitoring is implemented with a programmable

leaky bucket algorithFmu.nAcrteiofenreanlcSe pisedceisfigcnaattieodnas

âqualifiedâ if it is selected and its fractional frequency

offset is within the programmed range for a pro-

grammed soaking time. An auto reference elector

elects the most appropriate one from the reference

inputs according to the revertivity status, and each

referenceâs priority and qualification. If none of the

reference inputs is qualified, holdover or freerun

mode will be elected depending on the availability of

the holdover history.

Reference selection may be automatic, manual, or

hard-wired manual. In automatic reference selection

mode, the most appropriate one elected from the auto

reference elector will be the selected reference input.

In manual reference selection mode, user may spec-

ify any of the reference inputs as the selected refer-

ence input for external timing or holdover/freerun for

self-timing. In hard-wired manual mode, user can fast

switch using control pin SRCSW between two pre-

programmed reference inputs. The reference input

elected from the auto reference elector will not affect

the selected reference input in manual or hard-wired

manual mode.

In manual reference selection mode, the timing gen-

erator T4 may accept T0âs synchronized output as its

input.

Timing Generator and Operation

Mode

The STC5423 includes two independent timing gen-

erates, T0 and T4, to provide the essential functions

for SETS. Each timing generator can individually

operate in Freerun, Synchronized, Pseudo-Hold-

over and Holdover mode. A timing generator is in

either external-timing or self-timing. In external timing,

PLL of the timing generator phase-locks to the

selected external reference input. In self-timing, the

PLL simply tunes the clock synthesizers to a given

fractional frequency offset. Synchronized mode is in

external timing. PLLâs loop bandwidth may be pro-

grammed individually to vary the timing generatorâs

filtering function. Conversely, freerun, pseudo-hold-

over and holdover modes are all in self-timing. When

selected reference and previous holdover history are

unavailable, such as in systemâs initialization stage,

freerun mode may be entered or used. When

selected reference input is unavailable but a long-

Page 14 of 60 TM114 Rev: 1.4

Date: October 24, 2011

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