STC5423 Datasheet, PDF (15/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5423
Synchronous Clock for SETS
Data sheet
term holdover history accumulated in previous syn-
chronized mode is available, holdover mode may be
entered or used. STC5423 may enter pseudo-hold-
over using short-term frequency history. In STC5423,
the freerun clock is derived from the MCLK (external
oscillator) and digitally calibrated to compensate the
external oscillator’s accuracy offset. STC5423 also
allow users to program and manipulate the holdover
history accumulators.
Phase Synchronization
In synchronized mode, the phase relationship
between the selected reference input and the clock
output maybe phase arbitrary or frame phase align for
T0 timing generator. Frame phase align is enabled
when bit Phase Align of the register Control Mode is
set to “Align” and the reference input is at 8kHz. For
timing generator T4, the phase relationship is only
phase arbitrary. It allows an arbitrary phase relation to
be rebuilt during reference switch to minimize the
downstream clock’s phase transient. In this condition,
the STC5423 can provide hit-less switching if both
references are traced to the same clock source (e.g.,
PRC).
A maximum frequency ramp may be programmed to
minimize the ramp changing of fractional frequency
offset in case the new selected reference is not traced
to the same source. This feature restrains the fre-
quency transient which may cause the pull-out-of-lock
of the downstream network elements.
Clock Outputs
The STC5423 generates 9 synchronized clock out-
puts: 2 differential clock outputs (LVPECL or LVDS)
CLK1 and CLK2, 5 clock outputs CLK3 to CLK7
(LVCMOS), one 8kHz and one 2kHz frame pulse
clock outputs (LVCMOS). CLK1~CLK7 can be
derived from synthesizer G₁~G₇ through T0 path,
respectively, in which CLK3~CLK7 can also be
derived from synthesizer G_T4 through T4 path. Frame
pulse clock outputs are derived from synthesizer F.
See Figure 1 for functional details. Frequency of clock
outputs CLK1~CLK7 is programmable by program-
ming frequency of synthesizers from 1MHz up to
156.25MHz, in 1kHz step. Each of the synthesizers
has different default frequency value. The STC5423
allows the user to program the phase skew of each
clock synthesizer, up and down 50ns in roughly
0.024ns step to adjust the phase of clock outputs.
Frame pulse clock synthesizer generates frame pulse
clock outputs CLK8FKuanncdtioCnLKa2l KSpaet cfriefiqcuaetnicoynof
8kHz and 2kHz. The duty-cycle of CLK8K and CLK2K
is programmable.
Redundant Design
Timing generator T0 supports multiple-master oper-
ation for redundant applications to allow system
protection against the failure of the single part.
In multiple-master configuration, all units work as
masters. If the bit Phase Align of the register Control
Mode is set to “Align” and frequency of the selected
reference input is 8kHz, frame phase alignment is
enabled for T0 timing generator only. Clock outputs of
all the units will keep in frame phase alignment. In
order to meet same synchronization requirement,
each unit should use same parameter setup including
loop bandwidth.
Control Interfaces
The STC5423’s control interfaces are composed of
hardwire control pins and the bus interface. They
provide application access to the STC5423’s internal
control and status registers. This bus interface may
be configured among four type of micro-controller
interfaces, 3 of them are in parallel (Intel, Motorola,
Multiplexed) and one in serial (SPI). The selection of
the bus interface is pin-controlled.
Field Upgradability
The STC5423 supports Field Upgradability which
allows the user to load size of 7600 byte firmware
configuration data (provided as per request) via bus
interface. It provides the user a flexible field solution
for different applications.
Advantage and Performance
The kernel of each timing generator is a DSP-based
PLL. In STC5423, all internal modules are either digi-
tal or numerical, including the phase detectors, filters,
and clock synthesizers. The revolutionary pure-digital
design makes the timing generator become an accu-
rate and reliable deterministic system. This modern
technology removes any external part except the
external oscillator. It provides excellent performance
and reliability to STC5423. A well-chosen oscillator
will make STC5423 meet all the synchronization
requirements. Short-term stability associated with the
Page 15 of 60 TM114 Rev: 1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011