STC5423 Datasheet, PDF (38/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Event4: T0 timing generator’s event out is asserted
Event5: T4 selected reference changed in auto-selection mode
Event6: T4 PLL status changed
Event7: T4 timing generator’s event out is asserted
STC5423
Synchronous Clock for SETS
Data sheet
Default value: 0
Interrupt_Config, 0x1C (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0x1C
Not used
Configures the interrupt pin EVENT_INTR.
Active signal level
Sets the signal level in active mode.
0 = active low. 1 = active high
Idle mode
Specify the state of pin EVENT_INTR when no interrupt event occurs.
0 = tri-state. 1 = logic inactive
Default value: 0
Hard_Wired_Switch_Pre_Selection, 0x1D (R/W)
Bit1
Idle mode
Bit0
Active signal
level
Address
0x1D
Bit7
Bit6
Bit5
Bit4
Pre-selected reference number 2
Bit3
Bit2
Bit1
Bit0
Pre-selected reference number 1
Pre-selects reference number 1 and reference number 2 in hard-wired manual reference selection mode (T0
timing generator only). This mode is controlled by pin SRCSW. When pin SRCSW is LOW, reference number 1
is pre-selected. When pin SRCSW is HIGH, reference number 2 is pre-selected.
Default value: 0
Field Value
0
1
2
3~12
13
14
15
Selection
Freerun
Ref1
Ref2
Reserved
Holdover
Pseudo Holdover
Reserved
Page 38 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011