STC5423 Datasheet, PDF (48/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5423
Synchronous Clock for SETS
Data sheet
Selects clock output CLK2 derived from synthesizer G₂ or put in tri-state.
Default value: 0
CLK3_Sel, 0x53 (R/W)
Bits 2 ~ 0
0, 2, 3
1
CLK2 Synthesizer Select
Put CLK2 in tri-state mode
Synthesizer G₂
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x53
Not used
CLK3 Synthesizer Select
Selects the clock output CLK3 derived from synthesizer G₃ (T0) or synthesizer G_T4(T4). Signal level of CLK3 is
LVCMOS.
Bits 1 ~ 0
0
1
2
3
CLK3 Synthesizer Select
Put CLK3 in tri-state mode
Synthesizer G₃ (T0)
Reserved
Synthesizer G_T4 (T4)
Default value: 0
CLK4_Sel, 0x54 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x54
Not used
CLK4 Synthesizer Select
Selects the clock output CLK4 derived from synthesizer G₄ (T0) or synthesizer G_T4(T4). Signal level of CLK4 is
LVCMOS.
Bits 1 ~ 0
0
1
2
3
CLK4 Synthesizer Select
Put CLK4 in tri-state mode
Synthesizer G₄ (T0)
Reserved
Synthesizer G_T4 (T4)
Default value: 0
CLK5_Sel, 0x55 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x55
Not used
CLK5 Synthesizer Select
Page 48 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011