STC5423 Datasheet, PDF (22/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5423
Synchronous Clock for SETS
Data sheet
Manual Reference Selection Mode
In manual reference selection mode, the user may
select the reference manually. This mode is selected
at the Control Mode. The reference is selected by
writing to the register Manual Select Ref. The user
may also has the device enter freerun, pseudo-hold-
over or holdover manually by writing to the register
Manual Select Ref. In addition, T4 may select T0’s
output as the selected reference.
Hard-Wired Manual Reference Selection
Besides the manual reference selection mode, the
STC5423 provides a special mode to switch between
two pre-selected reference directly from a dedicated
pin SRCSW. The two pre-selected references are
configured at the register Hard Wired Switch Pre
Selection. It can make the device enter the freerun,
pseudo-holdover or holdover by writing to the register
Hard Wired Switch Pre Selection. In this mode, the
pin SRCSW operates as a simple switch by setting
high or low. The status of pin SRCSW can be read
from the register SRCSW Status. Hard-wired manual
reference selection is for T0 timing generator only.
Clock Outputs Details
The STC5423 generates 2 synchronized differential
(LVPECL or LVDS) clock outputs: CLK1 and CLK2; 5
LVCMOS clock outputs: CLK3~CLK7, one 8kHz and
one 2kHz frame pulse clock. Figure 5, Figure 6, and
Figure 7 respectively shows the clock output section
for CLK1/CLK2, CLK8K/CLK2K, and CLK3~CLK7.
Each output has individual clock output section con-
sist of synthesizer and clock generator. Clock genera-
tor of CLK1 or CLK2 has a LVPECL/LVDS driver to
produce differential output. Clock generators of
CLK3~CLK7 include a mux and a LVCMOS signal
driver. Clock generator of frame output CLK8K and
CLK2K consist of a duty cycle controller and a LVC-
MOS drive.
Clock Synthesizers
The STC5423 has 9 clock synthesizers, which of 8 is
disciplined by the timing generator T0: synthesizer
G₁~G₇ and one frame pulse clock synthesizer F. T4
disciplines a clock synthesizer G_T4. Clock synthesiz-
ers G₁~G₇ produce frequencies from 1MHz to
156.25MHz, in 1kHz steps. Phase skew of these syn-
thesizers are all programmable individually up and
down 50ns. CLK1 and CLK2 are derived from synthe-
sizer G₁ and G₂. CLK3 ~ CLK7 can be derived from
synthesizer G₃~G₇ r^Fes^upⁿe^cct^tiⁱv^oeⁿly,^aa^l l^Sso^peca^cn^ifb^ice^ad^te^iorivⁿed
from synthesizer G_T4, which is the synthesizer of tim-
ing generator T4 path. Synthesizer F produces frame
pulse at 8kHz and 2kHz with 50% duty cycle or pro-
grammable pulse width.
Clock Generators
Clock generator of CLK1 or CLK2 consist of a
LVPECL/LVDS signal driver. The signal level of clock
outputs CLK1 and CLK2 can be programmed to
either LVPECL or LVDS. Clock generators of
CLK3~CLK7 consist of a mux and a LVCMOS driver.
Each mux determines which synthesizer is selected
for generator to output clock. CLK3~CLK7 are all
LVCMOS. Signal level is driven from LVCMOS driver
in clock generator. The clock generator of frame pulse
output CLK8K and CLK2K contains a duty cycle con-
troller and a LVCMOS driver. The duty cycle is pro-
grammable at the register CLK8K Sel and CLK2K
Sel.
Synthesizer G₁
Synthesizer G₂
CLK1 Generator
LVPECL
/LVDS
DRIVER
CLK2 Generator
LVPECL
/LVDS
DRIVER
CLK1
1MHz ~ 156.25MHz
CLK2
1MHz ~ 156.25MHz
Figure 5:Output Clocks CLK1 and CLK2
Synthesizer G₃
Synthesizer G₄
Synthesizer G₅
Synthesizer G₆
Synthesizer G₇
CLK2 Generator
LVCMOS
DRIVER
CLK4 Generator
LVCMOS
DRIVER
CLK5 Generator
LVCMOS
DRIVER
CLK2 Generator
LVCMOS
DRIVER
CLK2 Generator
LVCMOS
DRIVER
CLK3
1MHz ~ 156.25MHz
CLK4
1MHz ~ 156.25MHz
CLK5
1MHz ~ 156.25MHz
CLK6
1MHz ~ 156.25MHz
CLK7
1MHz ~ 156.25MHz
Synthesizer G_T4
Figure 6:Output Clocks CLK3~CLK7
Page 22 of 60 TM114 Rev: 1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011