STC5423 Datasheet, PDF (50/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

CLK8K_Sel, 0x59 (R/W)
CLK2K_Sel, 0x5A (R/W)
STC5423
Synchronous Clock for SETS
Data sheet
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x59
0x5A
Invert
Invert
Duty Cycle Select
Duty Cycle Select
Selects duty cycle of the 8kHz and 2kHz frame clock for T0 timing generator. Both clock outputs CLK8K and
CLK2K derive from synthesizer F.
Bit 5 ~ 0
0
1~62
63
Duty Cycle Select
Disabled and tri-state
Pulse width 1 to 62 cycle of
155.52MHz
50% duty cycle
Bit 6
0
1
Default value: 0 (Tri-state, not inverted)
Field_Upgrade_Status, 0x70 (R)
Invert
Not inverted (frame on rising edge)
Inverted (frame on falling edge)
Address
Bit7
0x70
Bit6
Bit5
Bit4
Not used
Bit3
Bit2
Load_Complete
Bit1
READY
Bit0
Checksum
Checksum
Checks whether the 7600 bytes firmware configuration data is loaded successfully.
0 = Fail, 1 = Success
READY
Indicates if field upgrade is ready to begin, normally is set to 1 at 3 milliseconds (3ms) after the reset.
0 = Not ready
1 = Ready
Load_Complete
Indicates whether the loading of 7600 bytes firmware configuration data is complete.
0 = Not complete
1 = Complete
Field_Upgrade_Data, 0x71 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x71
Field upgrade of firmware configuration data
Writes the firmware configuration data (7600 bytes) to this register one byte at a time to complete data loading.
Only the last written byte can be read from this register, no matter how many times of reads performed.
Page 50 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011