STC5423 Datasheet, PDF (51/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5423
Synchronous Clock for SETS
Data sheet
Default value: 0
Field_Upgrade_Count, 0x72 (R)
Address
0x72
0x73
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Not used
Lower 8 bits of byte count for firmware configuration data
Higher 5 bits of byte count for firmware configuration data
Reads this register for how many bytes of 7600 bytes firmware configuration data has been loaded through the
register Field_Upgrade_Data.
Default value: 0
Field_Upgrade_Start, 0x74 (W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0x74
Start field upgrade
Bit1
Bit0
If bit READY of the register Field Upgrade Status is set to 1, user can write three values to this register con-
secutively, with no intervening read/writes from/to other registers to start the process of field upgrade. 7600
bytes firmware configuration data can only start loading after the three values are written successfully.
Order to Write
First
Second
Third
Bit 7 ~ 0
0x51
0x52
0x53
MCLK_Freq_Reset, 0x7F (R/W)
Register Writes:
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x7F
External oscillator frequency selection
Select accepted frequency of MCLK input by writing the associated value to this register three times consecu-
tively, with no intervening read/writes from/to other register. The associated values for the four accepted fre-
quency (10MHz, 12.8MHz, 19.2MHz, 20MHz) are as shown in table below. Three times of consecutive writes
will trigger internal soft-reset. Initial default accepted frequency for STC5423 is 12.8MHz. The accepted fre-
quency of MCLK input returns to 12.8MHz following any regular reset.
Perform writes at least 50us after the regular reset has done.
Written value is shown below:
Page 51 of 60 TM114 Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011