STC5423 Datasheet, PDF (49/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5423
Synchronous Clock for SETS
Data sheet
Selects the clock output CLK5 derived from synthesizer G₅ (T0) or synthesizer G_T4 (T4). Signal level of CLK5
is LVCMOS.
Bits 1 ~ 0
0
1
2
3
CLK5 Synthesizer Select
Put CLK5 in tri-state mode
Synthesizer G₅ (T0)
Reserved
Synthesizer G_T4 (T4)
Default value: 0
CLK6_Sel, 0x56 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x56
Not used
CLK6 Synthesizer Select
Selects the clock output CLK6 derived from synthesizer G₆ (T0) or synthesizer G_T4 (T4). Signal level of CLK6
is LVCMOS.
Bits 1 ~ 0
0
1
2
3
CLK6 Synthesizer Select
Put CLK6 in tri-state mode
Synthesizer G₆ (T0)
Reserved
Synthesizer G_T4 (T4)
Default value: 0
CLK7_Sel, 0x57 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x57
Not used
CLK7 Synthesizer Select
Selects the clock output CLK7 derived from synthesizer G₇ (T0) or synthesizer G_T4 (T4). Signal level of CLK7
is LVCMOS.
Bits 1 ~ 0
0
1
2
3
CLK7 Synthesizer Select
Put CLK7 in tri-state mode
Synthesizer G₇ (T0)
Reserved
Synthesizer G_T4 (T4)
Default value: 0
Page 49 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011