STC5423 Datasheet, PDF (23/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5423
Synchronous Clock for SETS
Data sheet
Synthesizer F
CLK8K Generator
Duty Cycle _LVCMOS
Controller _Driver
CLK2K Generator
Duty Cycle _LVCMOS
Controller
Driver
CLK8K
8kHz frame pulse
CLK2K
2kHz frame pulse
Figure 7:Output Clocks CLK8K and CLK2K
Clock Output Phase Alignment
If a clock output is derived from T0’s synthesizer (syn-
thesizer G₁~G₇) and has frequency that is integer
multiple of 8kHz, it is in phase alignment with the
frame pulse output CLK8K when synthesizer phase
skew is not programmed. Clock output derived from
T4’s synthesizer G_T4 has no phase alignment rela-
tionship with CLK8K.
Synthesizer Skew Programming
The STC5423 allows user to program the phase skew
of each clock synthesizer, up and down 50ns in
roughly 0.024ns steps. Since each of clock outputs is
dedicate derived from its synthesizer respectively,
adjust phase skew of the synthesizer will provide the
associated clock output a phase skew adjustment.
Phase skew of the 9 synthesizers may be pro-
grammed at the register Synth Skew Adj.
Clock Outputs
Available frequencies of CLK1~CLK7 are from 1MHz
to 156.25MHz, in 1kHz steps. Phase skew is adjust-
able at the associate synthesizer level. Two clock out-
puts, CLK8K and CLK2K, generate two frame pulse
clock at 8kHz and 2kHz.
Redundant Application
Timing generator T0 supports multiple-master opera-
tion for redundant applications to allow system
protection against single part failure.
Multiple Master Configuration
In multiple-master configuration, every unit locks to
the same reference input and has consistent loop
bandwidth settings. To enable phase alignment for all
master’s outputs, bit Phase Align of the register
Control Mode is set to “Align” and the reference
input has to be 8kHz.
Event Interrupts
Functional Specification
The STC5423 events shown following below are
interrupt events might occurred.
- Qualification status of the reference inputs change
- Selected reference of timing generator T0 changes in
automatic reference selection
- Selected reference of timing generator T4 changes in
automatic reference selection
- PLL status of timing generator T0 changes
- PLL status of timing generator T4 changes
- Out-Event of timing generator T0 asserts
- Out-Event of timing generator T4 asserts
The interrupt events can be read from the register
Interrupt Status. Each bit indicates one events. The
associate bit of the register Interrupt Status will not
be changed automatically when the event is cleared.
Therefore, the user need write ‘1’ to the associate bit
to erase the event.
The STC5423 has a pin EVENT_ INTR (pin 8) for
indicating the event interrupt occurrence. The pin
may be wired to user’s micro-controller. User can pro-
gram the register Interrupt Mask to decide which of
interrupt events will send an alarm to the micro-con-
troller by asserting the EVENT_INTR pin. User can
program at the register Interrupt Configuration to
specify the logic level (active high or low) of the pin
EVENT_INTR when it’s trigged by the interrupt event.
User may also program the register Interrupt Con-
figuration to define pin states as tri-state or logic
inactive when no interrupt event occurs.
Field Upgradability
The STC5423 supports field upgradability which
allows the user to load size of 7600 byte firmware
configuration data (provided as per request) via bus
interface. Field upgrade can only be performed at
least 3ms after reset.
1. User may read Bit READY of the register Field
Upgrade Status to check if field upgrade is ready
to start.
2. To begin the field upgrade, write to register Field
Upgrade Start three times consecutively, with no
intervening read/writes from/to other registers, see
the register Field Upgrade Start for details.
Page 23 of 60 TM114 Rev: 1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011