STC5423 Datasheet, PDF (32/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

ALE
CS
WR
RD
AD0-AD7
RDY
t_ALE
t_ALEd
t_ADs
t_ADh
t_CSs
STC5423
Synchronous Clock for SETS
Data sheet
t_CSd
t_WRB
t_CSh
Address
t_Ds
t_Dh
Data
t_RDYd1
t_RDYd2
t_RDY
t_WRBh
t_RDYd3
Figure 16: Multiplex Bus Write Timing
Table 13: Multiplex Bus Write Timing
Symbol
t_ALE
t_ALEd
t_ADs
t_ADh
t_CSs
t_WRB
t_CSh
t_CSd
t_Ds
t_Dh
t_RDYd1
t_RDYd2
t_RDY
t_WRBh
t_RDYd3
Description
ALE high time
Time between ALE falling edge and WR low
Address setup time
Address hold time
Write CS setup time
Write time
CS hold time
CS delay for multiple write/reads
Data setup time
Data hold time
CS low to RDY active
WR low to RDY low
RDY low time
WR hold after RDY high
RDY high-z delay after CS high
Min
Max
Unit
10
ns
0
ns
10
ns
10
ns
0
ns
40
ns
10
ns
50
ns
10
ns
10
ns
13
ns
40
ns
50
ns
0
ns
9
ns
Page 32 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011