STC5423 Datasheet, PDF (44/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

PLL_Status, 0x3C (R)
STC5423
Synchronous Clock for SETS
Data sheet
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x3C
HHA
DHT
Reserved
SAP
OOP
LOL
LOS
SYNC
SYNC Indicates whether synchronization has been achieved
0 = Not synchronized
1 = Synchronized
LOS
Loss of signal of the selected reference.
0 = No Loss
1 = Loss (Indicate loss of signal, freerun, and holdover)
LOL Loss of lock (Failure to achieve or maintain locking)
0 = No loss of lock
1 = Loss of lock
OOP
Out of pull-in range. Indicate the frequency offset of the selected reference input is out of pull-in range.
1 = Out of pull-in range
0 = In range
SAP
Indicates whether the clock output has stopped following the selected reference, caused by out of pull-
in range. Refer to bit OOP of the register Control_Mode (0x20).
1 = Stop following at pull-in range boundary
0 = Following
DHT
HHA
Device Holdover History Tracking
1 = Device holdover history is being tracked
0 = Device holdover history is not tracked, the value based on the latest available history
Holdover History Available. Config the register Control_Mode (0x20) to select which of holdover his
tory is used: Device Holdover History or User Specified History.
1 = Available
0 = Not available
Holdover_Accu_Flush, 0x3D (W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x3D
Not used
HO Flush
Writing to this register will perform a flush of the accumulated holdover history. Bit HO Flush determines which
history is flushed.
HO Flush:
0 = Flush and reset long term holdover history to 0
1 = Flush/reset both long term holdover history and the device holdover history to 0.
PLL_Event_Out, 0x3E (R/W)
Address
0x3E
Bit7
Event7
Bit6
Event6
Bit5
Event5
Bit4
Event4
Bit3
Event3
Bit2
Event2
Bit1
Event1
Bit0
Event0
Page 44 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011