STC5423 Datasheet, PDF (6/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5423 Pin Description
STC5423
Synchronous Clock for SETS
Data sheet
All I/O is LVCMOS, except for CLK1 and CLK2, which are LVPECL/LVDS.
Table 1: Pin Description
Pin Name
AVCC
AGND
VCC
GND
TRST
TCK
TMS
TDI
TDO
RST
MCLK
EVENT_INTR
REF1
REF2
CLK1_P
CLK1_N
CLK2_P
CLK2_N
CLK3
CLK4
CLK5
Pin #
I/O
Description
6,19,
5, 20,
12, 13,
16, 33,
39, 50,
61, 85,
86, 91
3.3V analog power input
Analog ground
3.3V power input
1, 11, 14,
15, 32,
38, 49,
62, 84,
87, 92
Digital ground
2
I JTAG boundary scan reset, active low
9
I JTAG boundary scan clock
7
I JTAG boundary scan mode selection
23
I JTAG boundary scan data input
21
O JTAG boundary scan data output
74
I Active low to reset the chip
10
I Master clock input (TCXO or OCXO)
8
O Event interrupt
46
I Reference input 1
47
I Reference input 2
34
O Clock output CLK1 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₁.
LVPECL or LVDS
35
O Clock output CLK1 negative. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₁.
LVPECL or LVDS
36
O Clock output CLK2 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₂.
LVPECL or LVDS
37
O Clock output CLK2 negative.1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₂.
LVPECL or LVDS
88
O Clock output CLK3. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₃ or Synthe-
sizer G_T4 (T4). LVCMOS.
89
O Clock output CLK4. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₄ or Synthe-
sizer G_T4 (T4). LVCMOS.
90
O Clock output CLK5. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₅ or Synthe-
sizer G_T4 (T4). LVCMOS.
Page 6 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011