STC5423 Datasheet, PDF (46/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Field Value
2
3
4
5
6
7
8
9
Default value: 0
Synth_Freq_Value 0x4B (R/W)
Synthesizer
Synthesizer G₂
Synthesizer G₃
Synthesizer G₄
Synthesizer G₅
Synthesizer G₆
Synthesizer G₇
Reserved
Synthesizer G_T4
STC5423
Synchronous Clock for SETS
Data sheet
Associated CLK Output
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Reserved
CLK3~CLK7
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x4B
0x4C
0x4D
Bits 0-7 of 18 bits Synthesizer Frequency Selection
Bits 15-8 of 18 bits Synthesizer Frequency Selection
Not used
Bits 17-16 of 18 bits Synthesizer
Frequency Selection
Selects synthesizer frequency value from 1MHz to 156.25MHz, in 1kHz steps, based on which synthesizer
index is selected at register Synth_Index_Select. CLK1~CLK7 is derived from synthesizer G₁~G₈ through T0
path, respectively, in which CLK3~CLK7 can also be derived from synthesizer G_T4 through T4 path.
This register is not writable for synthesizer F since its frequency is fixed at 8kHz and 2kHz. But phase skew of
synthesizer F is programmable at the register Synth_Skew_Select.
Default value varies with synthesizer index selection at the register Synth_Index_Select, refer to table below:
Synthesizer Index Selection
Synthesizer G₁
Synthesizer G₂
Synthesizer G₃
Synthesizer G₄
Synthesizer G₅
Synthesizer G₆
Synthesizer G₇
Synthesizer G_T4
Synth_Skew_Adj, 0x4E (R/W)
Associated CLK Output
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK3~CLK7
Default Value
155520 (155.52MHz)
125000 (125MHz)
19440 (19.44MHz)
38880 (38.88MHz)
2048 (2.048MHz)
25000 (25MHz)
50000 (50MHz)
2048 (2.048MHz)
Address
Bit7
0x4E
0x4F
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Lower 8 bits of Synthesizer Phase Skew Adjustment
Not used
Higher 4 bits of Synthesizer Phase Skew Adjustment
Page 46 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011