STC5423 Datasheet, PDF (39/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

SRCSW_States, 0x1E (R)
STC5423
Synchronous Clock for SETS
Data sheet
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x1E
Not used
Pin Status
Indicates status of pin SRCSW.
0 = Low, 1 = High
T0/T4_Tag_Select, 0x1F (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0x1F
Not used
Selects between timing generator T0 and T4 for the sharing registers 0x20~0x3F.
0 = T0; 1 = T4
Default value: 0
Control_Mode, 0x20 (R/W)
Bit1
Bit0
Tag_Select
Address
0x20
Bit7
Hard_Wired_Switch
Bit6
Reserved
Bit5
OOP
Bit4
Ref_Sel_Mode
Bit3
Revertive
Bit2
HO_Usage
Bit1
Internal Test
Bit0
Phase_ Align
Mode control bits for individual timing generator. Select between timing generator T0 and T4 at the register T0/
T4_Tag_select (0x1F).
Phase_Align (T0 timing generator only)
Determines the phase relationship is arbitrary or frame phase align.
0 = Arbitrary; 1 = Align (Frame phase align is only enabled when frequency of reference input is at
8kHz)
Internal Test
0 = Normal operation; 1 = Reserved
HO_Usage
Determines which holdover history is used.
0 = Device Holdover History (DHH); 1 = User specified history
Revertive
Selects the revertive mode or non-revertive mode of the auto-elector.
0 = Non-revertive; 1 = Revertive
Ref_Sel_Mode
Determines reference selection mode.
0 = Manual; 1 = Auto
This bit may be overridden by bit Hard_Wired_Switch of this register.
OOP
Page 39 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011