STC5423 Datasheet, PDF (19/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5423
Synchronous Clock for SETS
Data sheet
clock synthesizer in two conditions: First, it is used in
between the transition of two different operation
modes; second, it is used if LOS occurs when the
STC5423 operates in synchronized mode with manu-
ally reference selection. In addition, short-term history
is provided to perform failure diagnostics and evalua-
tions.
Long-Term History
Long-term history is an average frequency offset
between the clock output and MCLK which is filtered
internally using a weighted 3rd order low-pass filter
with the long time constant. The -3 dB filter response
point can be programmed from 0.15mHz to 1.3Hz by
writing to the register History Ramp. The history
value can be read from the register Long Term Accu
History.
Device Holdover History
Device holdover history is the history data used when
the STC5423 runs in holdover mode. It is acquired
from the long term history previously described. In
synchronized mode, when timing generator’s PLL
has locked to the selected reference input for over 15
minutes, the long term history is stored and further
updated as the device holdover history. If LOS or LOL
occurs, the device holdover history will stay at the lat-
est updated value until re-enter the synchronized
mode and the PLL locks to the new selected refer-
ence input for another 15 minutes. Set bit HO_Usage
of the register Control Mode to select using device
holdover history. Its value can be read from the regis-
ter Device Holdover History.
User-Specified History
The STC5423 allows user to provide the history data
created from their own sophisticated history accumu-
lation algorithms by writing to the register User Spec-
ified History. Set bit HO_Usage of the register
Control Mode to select using user specified holdover
history. Its value can be also read from the register
User Specified History.
Phase-Locked Loop Status Details
The register PLL Status contains the detailed status
of the PLLs, including the signal activity of the
selected reference, the synchronization status, and
the availability of the holdover histories.
SYNC bit
In external-timing mode, this bit indicates the
achievement of syncFhuronnciztaiotionna.lTShpisebcitifwicilal tniootnbe
asserted in self-timing mode.
LOS bit
In external-timing mode, this bit indicates the loss of
signal on the selected reference. This bit will not be
asserted in self-timing mode.
LOL bit
In external-timing mode, the bit will be set if the PLL
fails to achieve or maintain lock to the selected refer-
ence. This bit will not be asserted in self-timing mode.
This bit is also not complementary to the SYNC bit.
Both bits will not be asserted when the PLL is in the
pull-in process. The pull-in process usually occur
when switch to a new selected reference or recover
from the LOS/LOL.
OOP bit
This bit indicates that the selected reference is out of
the pull-in range. This is meaningful only if in exter-
nal-timing mode. This bit will not be asserted in self-
timing mode. The frequency offset is relative to the
digitally calibrated freerun clock.
SAP bit
This bit when set indicates that the PLL’s output
clocks have stopped following the selected reference
because the frequency offset of the selected refer-
ence is out of pull-in range (OOP). The user can write
to the register Control Mode to program whether the
PLL should follow the selected reference outside of
the specified pull-in range or just stay within the pull-
in range boundary.
DHT bit
This bit indicates whether the device holdover history
is tracking on the current selected reference (updat-
ing by the long-term history).
HHA bit
This bit indicates the availability of the holdover his-
tory, which may be either the user provided history or
the device holdover history.
Reference Inputs Details
The STC5423 accepts 2 external reference inputs at
8kHz, 64kHz, 1.544MHz, 2.048MHz, 19.44MHz,
38.88MHz, 77.76MHz, 6.48MHz, 8.192MHz,
16.384MHz, 25MHz, 50MHz or 125MHz. The two ref-
Page 19 of 60 TM114 Rev: 1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011