STC5423 Datasheet, PDF (4/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5423
Synchronous Clock for SETS
Data sheet
Table of Figures
Figure 1: Functional Block Diagram................................................................................................................... 1
Figure 2: Activity Monitor ................................................................................................................................. 20
Figure 3: Reference Qualification Scheme ...................................................................................................... 21
Figure 4: Automatic Reference Elector States................................................................................................. 21
Figure 5: Output Clocks CLK1 and CLK2 ........................................................................................................ 22
Figure 6: Output Clocks CLK3~CLK7.............................................................................................................. 22
Figure 7: Output Clocks CLK8K and CLK2K ................................................................................................... 23
Figure 8: SPI Bus Timing, Read access (Pin CLKE = Low) ............................................................................ 25
Figure 9: SPI Bus Timing, Read access (Pin CLKE = High) .......................................................................... 26
Figure 10: SPl Bus Timing, Write access ....................................................................................................... 26
Figure 11: Motorola Bus Read Timing ............................................................................................................ 27
Figure 12: Motorola Bus Write timing ............................................................................................................. 28
Figure 13: Intel Bus Read Timing ................................................................................................................... 29
Figure 14: Intel Bus Write Timing ................................................................................................................... 30
Figure 15: Multiplex Bus Read Timing............................................................................................................ 31
Figure 16: Multiplex Bus Write Timing ............................................................................................................ 32
Figure 17: Noise Transfer Functions .............................................................................................................. 54
Figure 18: Power and Ground ........................................................................................................................ 56
Page 4 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011