STC5423 Datasheet, PDF (1/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5423
Synchronous Clock for SETS
Data sheet
Description
Features
Functional Specification
The RoHS 6/6 compliant STC5423 is a single chip clock
synchronization solution for applications in SDH/SETS,
SONET, and Synchronous Ethernet network elements. The
device is fully compliant with ITU-T G.813 option 1 and 2,
G.8262 EEC option1 and 2, Telcordia GR1244 and GR253.
The STC5423 accepts 2 clock reference inputs and gener-
ates 9 synchronized clock outputs including two frame
pulse outputs at 8kHz and 2kHz. Synchronized clock out-
puts may be programmed for a wide variety frequencies
from 1MHz up to 156.25MHz, in 1kHz steps. Reference
inputs are individually monitored for activity and quality.
Reference selection may be automatic, manual, hard-wired
manual.
Two independent timing generators, T0 and T4, may oper-
ate in the Freerun, Synchronized, Pseudo Holdover and
Holdover mode. Each timing generator includes a DSP-
based PLL. Synchronized mode is external timing while fre-
erun, pseudo holdover and holdover mode are self-timing.
DSP-based PLL technology removes any external part
except the oscillator. It provides excellent performance and
reliability to STC5423.
The STC5423 is clocked by an external oscillator (TCXO or
OCXO). Using a well-chosen external oscillator ensures the
STC5423 meet the required specifications and standards.
- Complies with ITU-T G.813 opt1 and opt2, G.8262 EEC
opt1 and opt2, Telcordia GR1244 and GR253 (Stratum3/
4E/4/SMC)
- Two timing generators, T0 and T4; T4 may locks to T0’s
synchronized output
- Supports multiple master redundant application (T0 only)
- Accepts external oscillator at frequency of 10MHz,
12.8MHz, 19.2MHz,or 20MHz with programming
- Accepts 2 clock reference inputs
- Reference inputs are automatically frequency detected;
each is monitored for activity and quality
- Supports automatic, manual, and hard-wired manual ref-
erence selection
- Outputs 9 synchronized clock outputs, including 2 frame
pulse clocks
- 9 independent clock synthesizers
- Phase-align or hit-less reference locking/switching
- Programmable loop bandwidth, from 0.1Hz to 100Hz
- Programmable phase skew in synthesizer level
- Supports bus interface: Intel, Motorola, Multiplex, SPI
- Single 3.3V operation
- IEEE 1149.1 JTAG boundary scan
- Available in TQFP100 package
SRCSW
Ref Clk
2
2 LVCMOS
OCXO
TCXO
T0 Timing
Generator
Ref
Monitor
T4 Timing
Generator
Synthesizer G₁
Synthesizer G₂
Synth ^8kHz
F
2kHz
Synthesizer G₃
Synthesizer G₄
Synthesizer G₅
Synthesizer G₆
Synthesizer G₇
Synthesizer G_T4
µP Interface
Figure 1:Functional Block Diagram
CLK1, LVPECL/LVDS
CLK2, LVPECL/LVDS
CLK8K
CLK2K
CLK3
CLK4
CLK5
CLK6
CLK7
Page 1 of 60 TM114 Rev: 1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011