STC5423 Datasheet, PDF (7/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Pin Name
CLK6
CLK7
CLK8K
CLK2K
SRCSW
MPU_MODE0
MPU_MODE1
MPU_MODE2
CS
WR
RD
ALE/SCLK
RDY
A0/SDI
A1/CLKE
A2
A3
A4
A5
A6
AD0/SDO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Pin #
93
94
30
31
18
60
59
58
70
71
72
73
75
69
68
67
66
65
64
63
83
82
81
80
79
78
77
76
STC5423
Synchronous Clock for SETS
Data sheet
Table 1: Pin Description
I/O
Description
O Clock output CLK6. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₆ or Synthe-
sizer G_T4 (T4). LVCMOS.
O Clock output CLK7. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G₇ or Synthe-
sizer G_T4 (T4). LVCMOS.
O 8kHz frame pulse signal, 50% duty cycle or programmable pulse width (T0)
O 2kHz frame pulse signal, 50% duty cycle or programmable pulse width (T0)
I Hard-wired manual reference input pre-selection
I Bus interface: Intel, Motorola, Multiplexed, SPI
I
I
I SPI bus chip select
I Write access for Intel, Motorola and Multiplex bus interface
I Read access for Intel and Multiplex bus interface
I ALE: Address latch enable for Multiplex bus interface
SCLK: Clock edge selection for SPI
O Ready/Data Acknowledge for Intel, Motorola and Multiplex bus interface
I A0~A6: Address pins for bus interface Intel and Motorola
I
SDI: SPI bus data input
I
CLKE: Clock edge selection for SPI
I
I
I
I
I/O AD0~AD7: Bus interface Intel and Motorola data pins
Multiplex data and address pins
I/O
I/O ^{SDO: SPI bus data output}
I/O
I/O
I/O
I/O
I/O
Page 7 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011