STC5423 Datasheet, PDF (10/60 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5423
Synchronous Clock for SETS
Data sheet
Table 2: Register Map
Addr
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x3C
0x3D
0x3E
0x3F
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x59
0x5A
0x70
0x71
0x72
0x73
0x74
0x7F
Reg Name
Short_Term_Accu_History
User_Specified_History
History_Ramp
Ref_Priority_Table
PLL_Status
Holdover_Accu_Flush
PLL_Event_Out
PLL_Event_In
Synth_Index_Select
Synth_Freq_Value
Synth_Skew_Adj
CLK1/2_Signal_Level
CLK1_Sel
CLK2_Sel
CLK3_Sel
CLK4_Sel
CLK5_Sel
CLK6_Sel
CLK7_Sel
CLK8K_Sel
CLK2K_Sel
Field_Upgrade_Status
Field_Upgrade_Data
Field_Upgrade_Count
Field_Upgrade_Start
MCLK_Freq_Reset
Bits
31-0
Type
Description
R Short term Accumulated History
31-0 R/W User programmed holdover history
7-0
7-0
7-6,
4-0
0
7-0
7-0
3-0
17-0
R/W Controls long term history and short term history accumulation
bandwidth and the locking stage’s frequency ramp control
R/W REF1-2 selection priority
R PLL status. SYNC, LOS, LOL, OOP, SAP, DHT, HHA
W Flush/reset the long-term history and the device holdover history
R/W PLL event out (Reserved)
R/W PLL event in: Relock
R/W Determines which synthesizer is selected for setting frequency
value and adjusting phase skew
R/W Selects synthesizer frequency value from 1MHz to 156.25MHz, in
1kHz steps, based on which synthesizer index is selected at the reg-
ister Synth_Index_Select
11-0
1-0
1-0
1-0
1-0
1-0
1-0
1-0
1-0
6-0
6-0
2-0
7-0
12-0
R/W Adjusts phase skew for the synthesizer, based on which synthesizer
index is selected at the register Synth_Index_Select
R/W Selects the signal level (LVPECL or LVDS) for clock outputs CLK1
and CLK2
R/W Selects synthesizer G₁ or enable tri-state for CLK1
R/W Selects synthesizer G₂ or enable tri-state for CLK2
R/W Selects synthesizer (G₃ or G_T4) or enable tri-state for CLK3
R/W Selects synthesizer (G₄ or G_T4) or enable tri-state for CLK4
R/W Selects synthesizer (G₅ or G_T4) or enable tri-state for CLK5
R/W Selects synthesizer (G₆ or G_T4) or enable tri-state for CLK6
R/W Selects synthesizer (G₇ or G_T4) or enable tri-state for CLK7
R/W 8kHz frame pulse clock output duty cycle and frame edge selection
R/W 2kHz frame pulse clock output duty cycle and frame edge selection
R Indicates the status of field upgrade process
R/W Loads 7600 bytes of firmware configuration data
R Counts byte numbers that have been loaded
7-0
W Writes three values consecutively to start the field upgrade process
7-0 R/W Select the frequency of the external oscillator
Note 1: Timing generator T0 and T4 share register 0x20 ~ 0x3F. Register 0x1F selects between T0 and T4 for
the sharing registers 0x20~0x3F.
Page 10 of 60 TM114
Rev:1.4
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: October 24, 2011