EPM240_10 Datasheet, PDF (84/88 Pages) Altera Corporation – MAX II Device Family Data

5–26
Chapter 5: DC and Switching Characteristics
Referenced Documents
Table 5–34. MAX II JTAG Timing Parameters (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
tJP SU
JTAG port setup time (2)
8
—
ns
tJP H
JTAG port hold time
10
—
ns
tJP CO
JTAG port clock to output (2)
—
15
ns
tJP Z X
JTAG port high impedance to valid output (2)
—
15
ns
tJP XZ
JTAG port valid output to high impedance (2)
—
15
ns
tJS SU
Capture register setup time
8
—
ns
tJS H
Capture register hold time
10
—
ns
tJS CO
Update register clock to output
—
25
ns
tJS Z X
Update register high impedance to valid output
—
25
ns
tJS XZ
Update register valid output to high impedance
—
25
ns
Notes to Table 5–34:
(1) Minimum clock period specified for 10 pF load on the TDO pin. Larger loads on TDO will degrade the maximum TCK
frequency.
(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V
LVTTL/LVCMOS and 1.5-V LVCMOS, the tJPSU minimum is 6 ns and tJPCO, tJPZX, and tJPXZ are maximum values at 35 ns.
Referenced Documents
This chapter references the following documents:
■ I/O Structure section in the MAX II Architecture chapter in the MAX II Device
Handbook
■ Hot Socketing and Power-On Reset in MAX II Devices chapter in the MAX II Device
Handbook
■ Operating Requirements for Altera Devices Data Sheet
■ PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook
■ Understanding and Evaluating Power in MAX II Devices chapter in the MAX II Device
Handbook
■ Understanding Timing in MAX II Devices chapter in the MAX II Device Handbook
■ Using MAX II Devices in Multi-Voltage Systems chapter in the MAX II Device
Handbook
MAX II Device Handbook
© August 2009 Altera Corporation