EPM240_10 Datasheet, PDF (83/88 Pages) Altera Corporation – MAX II Device Family Data

Chapter 5: DC and Switching Characteristics
5–25
Timing Model and Specifications
Table 5–33. MAX II Maximum Output Clock Rate for I/O
MAX II / MAX IIG
I/O Standard
3.3-V LVTTL
304
3.3-V LVCMOS
304
2.5-V LVTTL
220
2.5-V LVCMOS
220
1.8-V LVTTL
200
1.8-V LVCMOS
200
1.5-V LVCMOS
150
3.3-V PCI
304
–3 Speed
Grade
304
304
220
220
200
200
150
304
–4 Speed
Grade
304
304
220
220
200
200
150
304
–5 Speed
Grade
304
304
220
220
200
200
150
304
–6 Speed
Grade
304
304
220
220
200
200
150
304
MAX IIZ
–7 Speed
Grade
304
304
220
220
200
200
150
304
–8 Speed
Grade
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
JTAG Timing Specifications
Figure 5–6 shows the timing waveforms for the JTAG signals.
Figure 5–6. MAX II JTAG Timing Waveforms
TMS
TDI
TCK
TDO
Signal
to be
Captured
Signal
to be
Driven
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPZX
t_JSSU
t_JPCO
t_JSH
t_JSZX
t_JSCO
t_JPH
t_JPXZ
t_JSXZ
Table 5–34 shows the JTAG Timing parameters and values for MAX II devices.
Table 5–34. MAX II JTAG Timing Parameters (Part 1 of 2)
Symbol
Parameter
Min
Max
Unit
t_JCP (1)
t_{JC H}
t_{JC L}
TCK clock period for V_CCIO1 = 3.3 V
TCK clock period for V_CCIO1 = 2.5 V
TCK clock period for V_CCIO1 = 1.8 V
TCK clock period for V_CCIO1 = 1.5 V
TCK clock high time
TCK clock low time
55.5
—
ns
62.5
—
ns
100
—
ns
143
—
ns
20
—
ns
20
—
ns
© August 2009 Altera Corporation
MAX II Device Handbook