EPM240_10 Datasheet, PDF (73/88 Pages) Altera Corporation – MAX II Device Family Data

Chapter 5: DC and Switching Characteristics
5–15
Timing Model and Specifications
Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 3)
MAX II / MAX IIG
MAX IIZ
–3 Speed –4 Speed –5 Speed –6 Speed –7 Speed –8 Speed
Grade
Grade
Grade
Grade
Grade
Grade
Symbol
Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Unit
tDDS
Data register data in 20 — 20 — 20 — 20 — 20 — 20 — ns
setup to data register
clock
t_DDH
Data register data in 20 — 20 — 20 — 20 — 20 — 20 — ns
hold from data
register clock
t_DP
Program signal to
0 — 0 — 0 — 0 — 0 — 0 — ns
data clock hold time
t_PB
Maximum delay
— 960 — 960 — 960 — 960 — 960 — 960 ns
between program
rising edge to UFM
busy signal rising
edge
t_BP
Minimum delay
20 — 20 — 20 — 20 — 20 — 20 — ns
allowed from UFM
busy signal going low
to program signal
going low
t_{PP M X}
Maximum length of — 100 — 100 — 100 — 100 — 100 — 100 µs
busy pulse during a
program
t_AE
Minimum erase signal 0 — 0 — 0 — 0 — 0 — 0 — ns
to address clock hold
time
t_EB
Maximum delay
— 960 — 960 — 960 — 960 — 960 — 960 ns
between the erase
rising edge to the
UFM busy signal
rising edge
t_BE
Minimum delay
20 — 20 — 20 — 20 — 20 — 20 — ns
allowed from the UFM
busy signal going low
to erase signal going
low
t_{E PM X}
Maximum length of — 500 — 500 — 500 — 500 — 500 — 500 ms
busy pulse during an
erase
t_DCO
Delay from data
— 5 — 5 — 5 — 5 — 5 — 5 ns
register clock to data
register output
© August 2009 Altera Corporation
MAX II Device Handbook