EPM240_10 Datasheet, PDF (78/88 Pages) Altera Corporation – MAX II Device Family Data

5–20
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–24. EPM570 Global Clock External I/O Timing Parameters (Part 2 of 2)
MAX II / MAX IIG
MAX IIZ
–3 Speed –4 Speed –5 Speed –6 Speed –7 Speed –8 Speed
Grade
Grade
Grade
Grade
Grade
Grade
Symbol Parameter Condition Min Max Min Max Min Max Min Max Min Max Min Max Unit
fCNT
Maximum
global clock
—
— 304.0 — 247.5 — 201.1 — 184.1 — 123.5 — 118.3 MHz
(1)
frequency for
16-bit counter
Note to Table 5–24:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input
pin maximum frequency.
Table 5–25 shows the external I/O timing parameters for EPM1270 devices.
Table 5–25. EPM1270 Global Clock External I/O Timing Parameters
MAX II / MAX IIG
–3 Speed Grade –4 Speed Grade –5 Speed Grade
Symbol
Parameter
Condition Min
Max
Min Max Min Max Unit
tPD1
Worst case pin-to-pin
10 pF
—
6.2
—
8.1
— 10.0 ns
delay through 1 look-up
table (LUT)
t_PD2
Best case pin-to-pin
10 pF
—
3.7
—
4.8
—
5.9
ns
delay through 1 LUT
t_SU
Global clock setup time
—
1.2
—
1.5
— 1.9 —
ns
tH
Global clock hold time
—
0
—
0
—
0
—
ns
tCO
Global clock to output
10 pF
2.0
4.6
2.0
5.9
2.0 7.3
ns
delay
t_CH
Global clock high time
—
166
—
216 — 266 —
ps
tCL
Global clock low time
—
166
—
216 — 266 —
ps
tCNT
Minimum global clock
—
3.3
—
4.0
— 5.0 —
ns
period for
16-bit counter
f_CNT
Maximum global clock
—
— 304.0 (1) — 247.5 — 201.1 MHz
frequency for 16-bit
counter
Note to Table 5–25:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
MAX II Device Handbook
© August 2009 Altera Corporation