EPM240_10 Datasheet, PDF (72/88 Pages) Altera Corporation – MAX II Device Family Data

5–14
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–20. t_XZ IOE Microparameter Adders for Slow Slew Rate
MAX II / MAX IIG
MAX IIZ
–3 Speed –4 Speed –5 Speed –6 Speed
Grade
Grade
Grade
Grade
–7 Speed
Grade
–8 Speed
Grade
Standard
Min Max Min Max Min Max Min Max Min Max Min Max Unit
3.3-V LVTTL 16 mA — 206 — –20 — –247 — 1,433 — 1,446 — 1,454 ps
8 mA — 891 — 665 — 438 — 1,332 — 1,345 — 1,348 ps
3.3-V LVCMOS 8 mA — 206 — –20 — –247 — 1,433 — 1,446 — 1,454 ps
4 mA — 891 — 665 — 438 — 1,332 — 1,345 — 1,348 ps
2.5-V LVTTL / 14 mA — 222 — –4 — –231 — 213 — 208 — 213 ps
LVCMOS
7 mA — 943 — 717 — 490 — 166 — 161 — 166 ps
3.3-V PCI
20 mA — 161 — 210 — 258 — 1,332 — 1,345 — 1,348 ps
1 The default slew rate setting for MAX II devices in the Quartus II design software is
“fast”.
Table 5–21. UFM Block Internal Timing Microparameters (Part 1 of 3)
MAX II / MAX IIG
MAX IIZ
–3 Speed –4 Speed –5 Speed –6 Speed –7 Speed –8 Speed
Grade
Grade
Grade
Grade
Grade
Grade
Symbol
Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Unit
tAC L K
Address register clock 100 — 100 — 100 — 100 — 100 — 100 — ns
period
t_{AS U}
Address register shift 20 — 20 — 20 — 20 — 20 — 20 — ns
signal setup to
address register clock
t_AH
Address register shift 20 — 20 — 20 — 20 — 20 — 20 — ns
signal hold to address
register clock
t_ADS
Address register data 20 — 20 — 20 — 20 — 20 — 20 — ns
in setup to address
register clock
t_ADH
Address register data 20 — 20 — 20 — 20 — 20 — 20 — ns
in hold from address
register clock
t_DCLK
Data register clock
100 — 100 — 100 — 100 — 100 — 100 — ns
period
t_DSS
Data register shift
60 — 60 — 60 — 60 — 60 — 60 — ns
signal setup to data
register clock
t_DSH
Data register shift
20 — 20 — 20 — 20 — 20 — 20 — ns
signal hold from data
register clock
MAX II Device Handbook
© August 2009 Altera Corporation