EPM240_10 Datasheet, PDF (76/88 Pages) Altera Corporation – MAX II Device Family Data

5–18
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
External Timing Parameters
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in Table 5–27 through Table 5–31.
f For more information about each external timing parameters symbol, refer to the
Understanding Timing in MAX II Devices chapter in the MAX II Device Handbook.
Table 5–23 shows the external I/O timing parameters for EPM240 devices.
Table 5–23. EPM240 Global Clock External I/O Timing Parameters (Part 1 of 2)
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed –6 Speed –7 Speed –8 Speed
Grade
Grade
Grade
Grade
Symbol Parameter Condition Min Max Min Max Min Max Min Max Min Max Min Max Unit
t_PD1
Worst case
10 pF — 4.7 — 6.1 — 7.5 — 7.9 — 12.0 — 14.0 ns
pin-to-pin
delay
through 1
look-up table
(LUT)
t_PD2
Best case
pin-to-pin
delay
through
1 LUT
10 pF — 3.7 — 4.8 — 5.9 — 5.8 — 7.8 — 8.5 ns
t_SU
Global clock
— 1.7 — 2.2 — 2.7 — 2.4 — 4.1 — 4.6 — ns
setup time
t_H
Global clock
—
0 — 0 — 0 — 0 — 0 — 0 — ns
hold time
t_CO
Global clock 10 pF 2.0 4.3 2.0 5.6 2.0 6.9 2.0 6.6 2.0 8.1 2.0 8.6 ns
to output
delay
t_CH
Global clock
— 166 — 216 — 266 — 253 — 335 — 339 — ps
high time
t_CL
Global clock
— 166 — 216 — 266 — 253 — 335 — 339 — ps
low time
t_CNT
Minimum
global clock
period for
16-bit
counter
— 3.3 — 4.0 — 5.0 — 5.4 — 8.1 — 8.4 — ns
MAX II Device Handbook
© August 2009 Altera Corporation