EPM240_10 Datasheet, PDF (46/88 Pages) Altera Corporation – MAX II Device Family Data

3–4
Chapter 3: JTAG and In-System Programmability
In System Programmability
Figure 3–1. MAX II Parallel Flash Loader
Flash
Memory Device
DQ[7..0]
A[20..0]
OE
WE
CE
RY/BY
TDI
TMS
TCK
TDO
TDO_U
TDI_U
TMS_U
TCK_U
SHIFT_U
CLKDR_U
UPDATE_U
RUNIDLE_U
USER1_U
Notes to Figure 3–1:
(1) This block is implemented in LEs.
(2) This function is supported in the Quartus II software.
MAX II Device
DQ[7..0]
A[20..0]
OE
WE
CE
RY/BY
Parallel
Flash Loader
Configuration
Logic
(1), (2)
Altera FPGA
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
In System Programmability
MAX II devices can be programmed in-system via the industry standard 4-pin IEEE
Std. 1149.1 (JTAG) interface. In-system programmability (ISP) offers quick, efficient
iterations during design development and debugging cycles. The logic, circuitry, and
interconnects in the MAX II architecture are configured with flash-based SRAM
configuration elements. These SRAM elements require configuration data to be
loaded each time the device is powered. The process of loading the SRAM data is
called configuration. The on-chip configuration flash memory (CFM) block stores the
SRAM element’s configuration data. The CFM block stores the design’s configuration
pattern in a reprogrammable flash array. During ISP, the MAX II JTAG and ISP
circuitry programs the design pattern into the CFM block’s non-volatile flash array.
The MAX II JTAG and ISP controller internally generate the high programming
voltages required to program the CFM cells, allowing in-system programming with
any of the recommended operating external voltage supplies (that is, 3.3 V/2.5 V or
1.8 V for the MAX IIG and MAX IIZ devices). ISP can be performed anytime after
V_CCINT and all V_CCIO banks have been fully powered and the device has completed the
configuration power-up time. By default, during in-system programming, the I/O
pins are tri-stated and weakly pulled-up to V_CCIO to eliminate board conflicts. The in-
system programming clamp and real-time ISP feature allow user control of I/O state
or behavior during ISP.
For more information, refer to “In-System Programming Clamp” on page 3–6 and
“Real-Time ISP” on page 3–7.
These devices also offer an ISP_DONE bit that provides safe operation when in-
system programming is interrupted. This ISP_DONE bit, which is the last bit
programmed, prevents all I/O pins from driving until the bit is programmed.
MAX II Device Handbook
© October 2008 Altera Corporation