EPM240_10 Datasheet, PDF (69/88 Pages) Altera Corporation – MAX II Device Family Data

Chapter 5: DC and Switching Characteristics
5–11
Timing Model and Specifications
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis independent of device
density. Table 5–15 through Table 5–22 describe the MAX II device internal timing
microparameters for logic elements (LEs), input/output elements (IOEs), UFM
blocks, and MultiTrack interconnects. The timing values for –3, –4, and –5 speed
grades shown in Table 5–15 through Table 5–22 are based on an EPM1270 device
target, while –6, –7, and –8 speed grade values are based on an EPM570Z device
target.
f For more explanations and descriptions about each internal timing microparameters
symbol, refer to the Understanding Timing in MAX II Devices chapter in the MAX II
Device Handbook.
Table 5–15. LE Internal Timing Microparameters
MAX II / MAX IIG
MAX IIZ
–3 Speed –4 Speed
Grade
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Symbol Parameter
tLUT
LE combinational
LUT delay
t_{CO M B}
Combinational
path delay
t_CLR
LE register clear
delay
t_PRE
LE register preset
delay
t_SU
LE register setup
time before clock
t_H
LE register hold
time after clock
t_CO
LE register clock-
to-output delay
t_{CL K H L}
Minimum clock
high or low time
t_C
Register control
delay
Min Max Min Max Min Max Min Max Min Max Min Max Unit
— 571 — 742 — 914 — 1,215 — 2,247 — 2,247 ps
— 147 — 192 — 236 — 243 — 305 — 309 ps
238 — 309 — 381 — 401 — 541 — 545 — ps
238 — 309 — 381 — 401 — 541 — 545 — ps
208 — 271 — 333 — 260 — 319 — 321 — ps
0 — 0 — 0 — 0 — 0 — 0 — ps
— 235 — 305 — 376 — 380 — 489 — 494 ps
166 — 216 — 266 — 253 — 335 — 339 — ps
— 857 — 1,114 — 1,372 — 1,356 — 1,722 — 1,741 ps
© August 2009 Altera Corporation
MAX II Device Handbook