EPM240_10 Datasheet, PDF (80/88 Pages) Altera Corporation – MAX II Device Family Data

5–22
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–27. External Timing Input Delay Adders (Part 2 of 2)
MAX II / MAX IIG
MAX IIZ
–3 Speed –4 Speed –5 Speed –6 Speed –7 Speed –8 Speed
Grade
Grade
Grade
Grade
Grade
Grade
I/O Standard
Min Max Min Max Min Max Min Max Min Max Min Max Unit
3.3-V LVCMOS Without Schmitt — 0 — 0 — 0 — 0 — 0 — 0 ps
Trigger
With Schmitt
Trigger
— 334 — 434 — 535 — 387 — 434 — 442 ps
2.5-V LVTTL / Without Schmitt — 23 — 30 — 37 — 42 — 43 — 43 ps
LVCMOS
Trigger
With Schmitt
Trigger
— 339 — 441 — 543 — 429 — 476 — 483 ps
1.8-V LVTTL / Without Schmitt — 291 — 378 — 466 — 378 — 373 — 373 ps
LVCMOS
Trigger
1.5-V LVCMOS Without Schmitt — 681 — 885 — 1,090 — 681 — 622 — 658 ps
Trigger
3.3-V PCI
Without Schmitt — 0 — 0 — 0 — 0 — 0 — 0 ps
Trigger
Table 5–28. External Timing Input Delay t_GLOB Adders for GCLK Pins
MAX II / MAX IIG
MAX IIZ
–3 Speed –4 Speed –5 Speed –6 Speed –7 Speed –8 Speed
Grade
Grade
Grade
Grade
Grade
Grade
I/O Standard
Min Max Min Max Min Max Min Max Min Max Min Max Unit
3.3-V LVTTL Without Schmitt — 0 — 0 — 0 — 0 — 0 — 0 ps
Trigger
With Schmitt
Trigger
— 308 — 400 — 493 — 387 — 434 — 442 ps
3.3-V LVCMOS Without Schmitt — 0 — 0 — 0 — 0 — 0 — 0 ps
Trigger
With Schmitt
Trigger
— 308 — 400 — 493 — 387 — 434 — 442 ps
2.5-V LVTTL / Without Schmitt — 21 — 27 — 33 — 42 — 43 — 43 ps
LVCMOS
Trigger
With Schmitt
Trigger
— 423 — 550 — 677 — 429 — 476 — 483 ps
1.8-V LVTTL / Without Schmitt — 353 — 459 — 565 — 378 — 373 — 373 ps
LVCMOS
Trigger
1.5-V LVCMOS Without Schmitt — 855 — 1,111 — 1,368 — 681 — 622 — 658 ps
Trigger
3.3-V PCI
Without Schmitt — 6 — 7 — 9 — 0 — 0 — 0 ps
Trigger
MAX II Device Handbook
© August 2009 Altera Corporation