EPM240_10 Datasheet, PDF (75/88 Pages) Altera Corporation – MAX II Device Family Data

Chapter 5: DC and Switching Characteristics
5–17
Timing Model and Specifications
Figure 5–4. UFM Program Waveforms
ARShft
ARClk
ARDin
DRShft
DRClk
DRDin
DRDout
OSC_ENA
Program
Erase
Busy
9 Address Bits
t_ASU
t_ACLK
t_ADS
t_AH
t_ADH
16 Data Bits
t_DSS
t_DCLK
t_DDS
t_DDH
t_DSH
t_OSCS
t_OSCH
t_PB
t_BP
t_PPMX
Figure 5–5. UFM Erase Waveform
ARShft
ARClk
ARDin
DRShft
DRClk
DRDin
DRDout
OSC_ENA
Program
Erase
Busy
t_ASU
t_ACLK
t_ADS
9 Address Bits
t_AH
t_ADH
t_OSCS
t_OSCH
t_EB
t_EPMX
t_BE
Table 5–22. Routing Delay Internal Timing Microparameters
MAX II / MAX IIG
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
Routing Min Max Min Max Min Max
t_C4
— 429 — 556 — 687
t_R4
— 326 — 423 — 521
t_{L O CA L}
— 330 — 429 — 529
Note to Table 5–22:
(1) The numbers will only be available in a later revision.
–6 Speed
Grade
Min Max
— (1)
— (1)
— (1)
MAX IIZ
–7 Speed
Grade
Min Max
— (1)
— (1)
— (1)
–8 Speed
Grade
Min Max Unit
— (1) ps
— (1) ps
— (1) ps
© August 2009 Altera Corporation
MAX II Device Handbook